A dislocation is created when there is sufficient stress to break silicon bonds and displace silicon atoms from their normal locations. This can occur during IC fabrication due to built-in device stress, as when oxide presses against a trench sidewall or when a high concentration of small boron atoms is implanted into a volume adjacent to a volume containing larger atoms. Or dislocations can be created when furnace slip takes place due to an excessive across-the-wafer temperature nonuniformity.

The dislocation is both a structural and an electrical defect. The tube-like opening down one side of a dislocation line can act as a diffusion pipe, accelerating and channeling the diffusion of dopant atoms and producing an IC device that is shorted or that breaks down at a low voltage. The electrical properties of a dislocation can cause several types of electrical failures because a dislocation promotes recombination, conduction, and generation.

If a dislocation is present in the base of a transistor, it decreases the gain because it acts as a trap and accelerates the recombination of minority charge carriers. The dislocation line is a conductive path, and the path becomes even more conductive when metal impurity atoms become attached to the silicon atoms along the dislocation. If a dislocation ends under a gate oxide, its enhanced conductive properties can cause gate oxide integrity failure.

The most common dislocation-induced failure mechanism is leakage. For an IC device to function properly, it must be possible to effectively change the silicon into an insulator by creating a depletion region. Conduction in an MOS transistor is turned off by applying a potential to the gate to create a depletion region by pushing the majority charge carriers out of the channel. A reverse-biased P/N junction prevents current flow because the reverse bias separates the holes and electrons and creates a depletion region at the junction. However, if a dislocation threads from one electrode, through a depletion region, to another electrode, then conduction along the dislocation line causes current to flow when it should not. This is one form of dislocation-induced leakage. Leakage also occurs when a dislocation within the depletion region acts as a line of generation centers, converting thermal energy into electron-hole pairs. The electric field within the depletion region causes the electrons to flow in one direction and the holes to flow in the other direction, and this constitutes the flow of a leakage current.

Whether or not a dislocation actually causes an IC device failure depends on where the dislocation is located. If the dislocation comes up under a field oxide, for example, it does no harm. But if it threads through a P/N junction, it can cause a leakage failure. If a wafer has a high incidence of leakage failures, failure analysis can be carried out by stripping off the IC pattern layers and applying a defect etch to the silicon surface (Fig. 1). Dislocation etch pits then show where the dislocations intersected the silicon surface. If the dislocation etch pits show no across-the-wafer pattern, but are consistently located at certain IC device structures, then the stress that created the dislocations was probably built-in device stress (Fig. 2). But if the dislocations are concentrated in a center spot (Fig. 3 & 4) or an edge pattern, then the stress that created the dislocations was probably furnace stress. Often a leakage failure map will suggest whether or not furnace slip has taken place. If wafer failure analysis shows a spatial correlation between a high dislocation density and a high leakage failure rate, then you can be virtually certain that it was the dislocations that caused the leakage.

Figure 1

Wafer surface after pattern removal and defect etching. Short shallow dislocation loops are consistently located at certain IC device structures. This indicates that the dislocations were probably produced by built-in device stress.

Figure 2

Wafer surface after pattern removal and defect etching. Dislocation etch pits are located along slip lines. This indicates that the dislocations were produced by a nonuniform temperature distribution during furnace processing.

Figure 3

Leakage failure map. This "four corners" leakage failure pattern for a <100> wafer indicates that the wafer probably slipped at the edges due to too-rapid edge-first heating during furnace processing.

Figure 4

Leakage failure map. This "center spot" leakage failure pattern indicates that the wafer may have slipped in the center due to too-rapid edge-first cooling during furnace processing.