Wafer Nanotopography

With the implementation of CMP planarization processes for Shallow Trench Isolation, the nanotopography of the silicon wafer is becoming a more significant factor to consider. Nanotopography is defined as the deviation of a surface within a spatial wavelength of around 0.2 to 20 mm. Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency. Nanotopography of the silicon wafer is dictated to a large extent by the polishing process. A true planetary, freefloating, double-sided polishing process that polishes both sides of a silicon wafer simultaneously technically achieves the best nanotopography and flatness results.

 


Description:

With the implementation of CMP planarization processes for Shallow Trench Isolation(1), the nanotopography of the silicon wafer is becoming a significant factor to consider.

Nanotopography is defined as “the deviation of a surface within a spatial wavelength of around 0.2 to 20 mm.”(2) This is a parameter that measures the front-surface, freestate topology of an area which can range in size from fractions of a millimeter to tens of millimeters. In this sense, nanotopography differs from front-referenced site flatness in that for nanotopography the wafer is measured in a free state, while for flatness it is referenced to a flat chuck. A wafer may have perfect flatness (in the classical definition of flatness), yet still have nanotopography. If a wafer has surface irregularities on the front and backside of the wafer, but front and back surfaces are parallel, the wafer has perfect flatness. However, the same wafer will exhibit nanotopography (Figure 1). Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency (Figure 2). As linewidths shrink, with non-uniform pattern density and with the use of hard pads for CMP, nanotopography may significantly degrade the dielectric film uniformity.(3,4)

Nanotopography is measured by two techniques: light scattering and interferometry. Light scattering tools typically employed for particle and surface-defect characterization can be used to measure the local slope change over the entire surface of the wafer. The local slope change may be integrated to yield height or topography information. Since the beam size can be on the order of fractions of a micron, nanotopography can be measured. Optical interference measurement is straightforward: a beam is split into two components; one component is reflected from the wafer surface, while the second is reflected from a reference mirror; the interference of the combination of the two beams is a measure of the topology of the wafer surface. With both techniques signal filtering is used to separate the low-wavelength features (i.e. warp) so that only the high-wavelength/low-frequency information, (i.e. the true surface nanotopography) is measured.

Role of Nanotopography in CMP:

The interaction between nanotopography upon film removal uniformity in CMP has been under extensive investigation by Boning and co-workers(5,6,7,8) and Tamura et al.(9) The primary effect of oxide uniformity removal is due to the hardness of the CMP pad. The fundamental concept is very simple: soft polishing pads conform to local topology variations (i.e. nanotopography) while hard pads do not. Figure 3, adapted from Boning et al.(6), illustrates this principle. Typically, a wafer has a characteristic nanotopography length (NL, shown in the top illustration of Fig. 3). The soft pad will conform over the nanotopography and maintain a uniform film. The hard pad will not conform to the nanotopography and produce a non-uniform film with high spots on the wafer surface having a thinner film and low spots having a thicker film. Traditionally soft pads have been used for film removal CMP. However, with the need for better planarization, because of more layers, smaller CD and for multi-function logic devices which have several different areas of varying pattern densities(10), stiff pads are required. To some extent, the effect of nanotopography can be minimized by using polishing additives, such as ceria particles(11). Nonetheless wafer nanotopography becomes increasingly important.

To understand the influence of nanotopography in CMP film removal uniformity, the concept of planarization length should be considered(5). The planarization length (PL) is the spatial length at which polishing cannot reduce the step height of a feature in the film thickness. This is illustrated in Figure 4. The important aspect to consider is when PL is less than NL the film uniformity is maintained. When PL is more than NL one finds nonuniform film removal. Two typical examples are shown in Fig. 3. The CMP process and the film uniformity specifications may be considered to determine the level of nanotopography required.

Impact of the Wafer:

Nanotopography of the silicon wafer is dictated to a large extent by the polishing process. For single-sided polished (SSP) wafers, the polishing process has been optimized to minimize nanotopography. In this process, to achieve good flatness, the wafer must be mounted or chucked against a flat reference block. Since the wafer backside is etched (not polished smooth), it has surface topology. Because of the fixturing process used to mount the wafers (e.g. wax mounting or vacuum chucking), the topology of the backside of the wafer and the fixturing surface and or adhesive/wax are
transmitted to the front side and causes nanotopography. The other technique of mounting a wafer (the one that is normally used in CMP), viz. free mounting, does not cause nanotopography formation, but also does not guarantee the wafer is made flat. The best flatness and nanotopography is obtained when the wafers are double-sided polished (DSP). The true, planetary, free-floating DSP polishing process polishes both sides of a silicon wafer simultaneously. Since the wafer is polished in a free state, nanotopography is minimized. Also, good flatness is achieved. Thus, both good flatness and nanotopography are produced. Figure 5 shows a comparison of SSP and DSP mounting techniques and how these affect nanotopography and flatness.

Figure 6 shows how SSP and DSP wafers affect CMP film removal uniformity. The CMP process employed (hard pad vs. soft pad) and the wafer type (SSP vs. DSP) interact with different levels of film removal uniformity. The correlation coefficients shown in this figure are taken from Boning et al.(6) They represent a measure of how much nanotopography correlates with film removal uniformity. A coefficient of 1 indicated that each high spot on the wafer surface corresponds with a local thin film (high removal or overpolish) and each low spot on the surface corresponds with a local thick film (low removal or underpolish). Conversely, a correlation coefficient of 0 indicates no correlation between nanotopography and film removal uniformity. It should be emphasized that the coefficient is not a measure of the actual uniformity, only the correlation between uniformity and nanotopography. The removal uniformity is generally better for the DSP wafer because it exhibits less nanotopography and hence less variation.

SunEdison Semiconductor has developed a planetary DSP polishing process that provides wafers with leading edge nanotopography and flatness characteristics that meet all of the increasingly demanding CMP requirements. While planetary DSP is technically the best method to achieve superior nanotopography and flatness, there are several barriers to practically implementing this method in the fab. These barriers include cost of ownership for DSP, issues related to running both a polished backside DSP and an etched backside wafer in their lines at the same time, such as electrostatic chuck problems, and in-line sensor calibration. SunEdison Semiconductor is actively exploring both planetary DSP and SSP methods that promise to achieve a good balance between nanotopography and flatness results and cost of ownership.

References:

  1. J. Schlueter, “Trench Warfare: CMP and Shallow Trench Isolation,” Semiconductor International, October 1999.
  2. SEMI DRAFT Document 3089: Guide for Reporting Wafer Nanotopography.
  3. K. V. Ravi “Wafer Flatness Requirements for Future Technologies,” Future Fab International, Issue 7, 207.
  4. C. Shan Xu, E. Zhao R. Jairath and W. Krusell, Electrochemical and Solid-State Letters, 1 (4) 181 (1998).
  5. B. Lee, D. Boning, W. Baylies, N. Poduje, P. Hester, Y. Xia, J. Valley, C. Koliopoulus, D. Hetherington, H. Sun, M. Lacy, “Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods,” Materials Research Society (MRS) Spring Meeting, San Francisco, CA, April 2001.
  6. D. Boning, B. Lee, W. Baylies, N. Poduje, P. Hester, J. Valley, C. Koliopoulos and D. Hetherington, “Characterization and Modeling of Nanotopography Effects on CMP,” International CMP Symposium 2000, Tokyo, Japan, Dec. 4, 2000.
  7. C. Oji, B. Lee, D. Ouma, T. Smith, J. Yoon, J. Chung, and D. Boning, “Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing,” J. Electrochem. Soc. 147 (11) 4307, Nov. 2000.
  8. B. Lee, T. Gan, D. Boning, P. Hester, N. Poduje, and W. Baylies, “Nanotopography Effects on Chemical Mechanical Polishing for Shallow Trench Isolation,” Advanced Semiconductor Manufacturing Conference, Boston, MA, Sept. 2000.
  9. N. Tamura, H. Niwa, M. Hatanaka, M. Kase, and T. Fukuda (Fujitsu Limited), “The Influence of Wafer Nanotopology on Residual Film Thickness Variation after Chemical Mechanical Planarization,” 197th ECS Meeting, Toronto, Ontario, Canada, May 2000.
  10. T. Tugbawa, T. Park, B. Lee, D. Boning, P. Lefevre, and L. Camilletti, “Modeling of Pattern Dependencies for Multi-Level Copper Chemical-Mechanical Polishing Processes,” Materials Research Society (MRS) Spring Meeting, San Francisco, CA, April 2001.
  11. B. Lee, D. Boning, L. Economikos, “A Fixed Abrasive CMP Model,” Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC 2001), pp. 395- 402, Santa Clara, March 2001.