Analog/Discrete

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the ntire lateral and vertical region between the wfer front and back sides.
S - Surface; the surface region of a silicon wafer (usually refers to top 10μ)
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturer's line.

Analog Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Cost Per Die, Productivity B Long cycle time and high processing cost due to long thermal treatment steps in the IC fab process that are exclusively designed for denuding. Starting polished wafer with built-in denuding and nucleation that does not rely on long thermal treatments in the IC fab process. MDZ

EPI
Furnace cycle time reduction or throughput increase.  Reduced thermal budget up to 35%. Saving in furnace capital expenditure or operation cost.
Device Die Yield, Reliability B Excessive PN junction leakage current due to OSF, heavy metallic contamination or oxygen precipitates in the sub-surface. Efficient gettering to effectively getter high levels of metals such as Copper, Nickel, and Iron. MDZ Improvement of device reliability.
Device Die Yield, Reliability S, B Diffusion of ungettered metals to the active device region, causing leakage or device short. Robust, consistent gettering independent of initial oxygen level and thermal history. Improves gate oxide integrity (GOI) issue. MDZ Yield increase up to 2%.
Device Die Yield S, B Furnace slip, dislocations, especially at high temperature steps such as buried layer diffusion and subsequent epi growth. Increase oxygen level to lock dislocations without allowing precipitates to grow large, improving slip resistance.  

Increase slip resistance by nitrogen doping.

Smooth edge.
MDZ

EPI

Annealed
Yield increase up to 1%.
Enhance RF Performance I The magnitude of the quality factor degradation of passives at high frequency is larger with the high carrier (low resistivity) density in the substrate, limiting the integration of passives with CMOS or BiCMOS DMOS. Higher resistivity lowers the parasitic substrate capacitance and eddy current loss in the substrate. High-Resistivity Polished Wafer

Annealed
Higher Q-factor of inductors and MIM capacitors at RF frequency.

 

Discrete Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Device Yield B, I Excess PN junction leakage current due to furnace slip, dislocations. Optimized oxygen concentration.

Controlled oxygen precipitation.

Smooth edge.

Optimized loading/unloading temperatures and ramping rates of thermal cycles.
MDZ

EPI
Increased device die yields from reduced leakage currents.
Device Yield, Enhance Reliability B, S, I Excess PN junction leakage due to OSFs, heavy impurity metallic contamination or oxygen precipitates in the sub-surface.

Diffusion of ungettered heavy impurity metals to the active device region.
Efficient gettering to effectively getter high levels of metals such as Copper, Nickel, and Iron.

Controlled oxygen precipitation with good precipitate-free zone.
MDZ

EPI
Increased device die yields from reduced leakage currents.
Device Yield B, I Loss of dies with the breakdown-blocking voltage lower than the rated voltage. Good uniformity of epi resistivity and thickness. EPI Increased BV die yields due to breakdown-voltage above the rated voltage
Device Yield B, I Loss of dies with high on-state resistance. Good uniformity of epi resistivity and thickness. EPI Increased Rds (on) yields of MOSFETs.

Increased hFE yield of bipolar.
Conduction power loss, high heat dissipation. B, I On-resistance needs to be lowered to decrease power loss.

Limitation to the lowest on-resistance of newer generation power devices.
Low resistivity substrate. Arsenic doped substrate.

Red phosphorus doped substrate.
Lower power consumption.

Improved power figure of merit without BV tradeoff.

Increased process design flexibility.