Memory

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications.  Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues.  Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the entire lateral and vertical region betweenthe wafer front and back sides.
S - Surface; the surface region of a silicon wafer (usually refers to top 10μ).
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufaturer's line.

DRAM Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Device Yield S Minimize impact of COP related yield degradation (leakage, trench to trench shorts (trench technology) and isolation failures). 1) Wafers completely free of COPs.

2) Wafers with COP free surface region.
Perfect Silicon

Ar Annealed
Yield improvement, reliability improvement.
Device Yield S Minimize effect of near surface oxygen precipitates (device leakages, trench to trench shorts (trench technology), isolation failures, and non-uniform RIE). Wafer with no near surface oxygen precipitates (denuded zone structure). MDZ

Optia

Ar Annealed
Improvement in device reliability.
Device Yield S Minimize impact of surface metals (device leakage, isolation failures, and non-uniform RIE). Wafer that has excellent intrinsic gettering. MDZ

Optia
Yield improvement, reliability improvement.

 

Flash Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Enhance Reliability, Device Yield B, S, I Tunnel Oxide quality is a critical requirement for flash.  Killer defect for leakage failure is point defect such as COP and Metal precipitation on TNOX layer. COP-free wafer with MDZ.  COP-free translates to defect-free material. Optia

MDZ

Perfect Silicon
MDZ provides robust gettering, which prevents metal contamination.

Optia provides COP-free options as Perfect Silicon.
Enhance Reliability, Device Yield B, I Flash device is extremely sensitive to COP defects and metal contamination.  Therefore, GOI is a critical concern. COP-free wafer with MDZ.  COP-free translates to defect-free material. Optia

MDZ

Perfect Silicon
MDZ provides robust gettering, which prevents metal contamination.

Optia provides COP-free options as Perfect Silicon.
Device Yield B, I Metal Contamination from backside grinding or dry-polishing. P/P+ Epi provides a good gettering solution. Optia

MDZ

P/P+ Epi
1) P+ material has minimum gettering requirement.

2) A polished wafer provides a cost advantage (Optia).

Optia has epi-like GOI and COP-free characteristics.

MDZ provides robust gettering, which prevents metal contamination.
Device Yield B, I Yield loss due to gate oxide integrity (GOI) issues. Rapid thermal process based on technology in which the oxygen precipitation behavior is controlled by manipulation of vacancy rather than oxygen concentration profiles. Optia

MDZ
Yield improvement up to 10%.
Processing Cost B, I Increased processing costs due to long thermal treatments. Optia wafers do not rely on thermal treatments in the IC fab process. Optia

MDZ
Reduce thermal budget up to 40%.

MDZ reduces cost of ownership (COO) due to lower thermal budget in the IC fab.
Enhance Reliability B, S, I Device loss due to metal contamination. Optia will effectively getter high levels of metals such as Copper, Nickel, and Iron. Optia

MDZ
Improvement in device reliability.
Device Yield B, S, I Crystal defect related yield and reliability degradation. Elimination of harmful crystal defects in the surface and bulk. Optia

MDZ
Yield improvement, reliability improvement.

Perfect Silicon crystal results in a defect-free wafer.
Device Yield B, I Yield loss due to uncontrolled precipitation of oxygen. Rapid thermal process based technology in which the oxygen precipitation behavior is controlled by manipulation of vacancy rather than ocygen concentration profiles. Optia

MDZ
MDZ provides required BMD densities that demonstrate uniform stacking faults and precipitate distribution.
Device Yield S, I Nanotopography and flatness issues. Need uniform flatness center-to-edge to print very small feature sizes. Optia Extend usable edge area, which increasesthe number of usable die per wafer.
Enhance Reliability, Device Yield B, I Stored charge leakage due to tunnel oxide quality. COP-free wafer with MDZ and OOBG. Optia

MDZ
Yield improvement, reliability improvement.