Processor/CMOS Logic

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications.  Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues.  Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the entire lateral and vertical region between the wafer front and back sides.
S - Surface; the surface regions of a silicon wafer (usually refers to the top 10μ).
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturer's line.

Processor Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Critical Dimension Scaling S Maintain dimension scaling to increase performance and functionality. Integration of ultra-flat wafer processing to improve site flatness and minimize wafer edge roll off. Epi (P/P+)

Epi (P/P++)

w/ caustic etch & advanced single side polish (200mm)
Improved site flatness enables photolithography process to print smaller critical dimensions.

Excellent nanotopography for critical dimension scaling and CMP uniformity.
High Device Yield for Aggressively Scaled Critical Dimension S, B Maintaining high yield with smaller feature size and increased device density. Epi on P+ or P++ substrate for COP-free and oxygen precipitate-free layer, gettering, and latch up resistance.

COP-free wafer with internal gettering and oxygen precipitate-free zone.

Epi on P- substrate for COP-free and oxygen precipitate-free layer.
Epi (P/P+)

Epi(P/P++)

Ar-Annealed

Optia
High Device Yield.
Device Die Yield, Reliability S, B Diffusion of ungettered metals to the active device region, causing leakage or device short. Robust, consistent gettering independent of the initial oxygen level and thermal history.  Improves gate oxide integrity (GOI) issue. MDZ

Optia
Yield increase up to 2%.
Enhance Performance S, I Increase transistor drive current to increase operating frequency. <100> notch/channel orientation. <100> notch oriented device layer 10% PMOS drive current enhancement through improved channel mobility.

 

CMOS Logic Solutions

Segment Drivers Bulk; Surface; Integration Problem Solution SunEdison Semiconductor Product or Process Benefits
Critical Dimension Scaling S Maintain dimension scaling to increase performance and functionality. Advanced Single Side Polish (200mm). Integration of ultra-flat wafer processing with:

Ar-Annealed

Optia

Epi (P/P+)

Epi (P/P-)
Enable dimension scaling with high device yield.
Device Yield S, B Eliminate wafer defect-related device yield loss. COP-free wafer with Internal Gettering and Oxygen Precipitate-free zone. Ar-Annealed

Optia

Epi (P/P+)

Epi (P/P-)
High Device Yield.
Radio Frequency CMOS S, B, I Integrate high quality factor passive components and isolate RF/analog components from digital CMOS High resistivity silicon.

High resistivity silicon on insulator.
Ar-Annealed ~100% increase in inductor Q-factor for 10x increase in resistivity.
Enhance Performance S, I Increase transistor drive current to increase operating frequency. <100> notch/channel orientation. Ar-Annealed

Optia

Epi (P/P+)

Epi (P/P-)
10% PMOS drive current enhancement through improved channel mobility.