Technical Articles

ARE YOU TAKING ADVANTAGE OF YOUR SILICON SUPPLIERS?

As appeared in European Semiconductor, July 2004 
Adobe Acrobat ® PDF Format (171KB). Posted with permission.

Technology change in the semiconductor market is forcing device makers to partner with silicon wafer manufacturers to achieve the performance needed to move forward. Those who take advantage of the new reality will realize a competitive edge and reap the subsequent rewards.

Pipeline Defects in Flash Devices Associated with Ring OSF

As appeared in Semiconductor Manufacturing, December 2003
Adobe Acrobat ® PDF Format (173KB). Posted with permission.

Pipeline defects were known to occur in both bipolar and CMOS devices. It is reported that a possible physical correlation exists between a type of etch pit pairs (EPP) and pipeline defects on an EEPROM device. The density of EPPs, and the density of pipeline defects, was found to be significantly reduced by a 900°C anneal in nitrogen prior to N+ oxidation,and lower arsenic dose and thinner nitride in LOCOS for field isolation.

Evaluating the effects of internal gettering in epi Si

As appeared in Solid State Technology, November 2003
Adobe Acrobat ® PDF Format (285KB). Posted with permission.

A rigorous study of the efficiency of internal gettering under different conditions, comparing it to external and p+ gettering, has shown it to be effective in p+ substrates with backside polysilicon. This is true when the density of oxygen precipitates is high and their size small. However, internal gettering is not effective for a low density of oxygen precipitates when using either p+ substrates or polysilicon.

A novel method to prepare wafers with very low COPs for bonded SOI

As appeared in Solid State Technology, March 2003
Adobe Acrobat ® PDF Format (224KB). Posted with permission.

The adoption of silicon-on-insulator (SOI) wafers is clearly part of the future of advanced semiconductor manufacturing, particularly in extending planar CMOS technology beyond sub-50nm gates. Yet, today the cost of SOI wafers is still a barrier for some applications. Presented here is a more cost-effective method — using high heating and cooling rates in a sequential hydrogen-argon rapid anneal — for producing silicon wafers, with low crystal defect counts, used to fabricate SOI wafers.

A HISTORY OF INDUSTRY INNOVATION: FACETED DISLOCATION-FREE CRYSTAL

As appeared in Semiconductor International, June 2001
Adobe Acrobat ® PDF Format (210KB). Posted with permission.

Dislocation-free growth of Czochralski-grown silicon crystals began in 1959 with a paper written by William Dash in which he showed how to eliminate edge dislocations originating from the seed or from thermal shock during the seeding operation.

BEST IF USED BY ... SHELF LIFE FOR SILICON WAFERS

As appeared in Semiconductor International, May 2001
Adobe Acrobat ® PDF Format (75KB). Posted with permission.

Silicon wafer users expect that the surface of the wafers they receive from wafer makers will meet all requirements for light point defects (LPDs), metals, grown-on film quality and cleanability regardless of the storage history of the wafers.

NEW EPITAXIAL WAFER DEVELOPMENTS ENHANCE DEVICE MANUFACTURERS' CAPABILITIES

As appeared in Semiconductor International, April 2001
Adobe Acrobat ® PDF Format (82KB). Posted with permission.

The business of SunEdison Semiconductor Electronic Materials, Inc. is to develop, manufacture and sell consistently high performing silicon wafers for selected segments and customers in the semiconductor industry.

VACANCY PROFILES EFFECTIVELY CONTROL OXYGEN BEHAVIOR IN SILICON

As appeared in Semiconductor International, March 2001
Adobe Acrobat ® PDF Format (35KB). Posted with permission.

Controlling oxygen behavior in silicon is undeniably one of the most important challenges in semiconductor materials engineering. In particular, control of oxygen precipitation is essential for the development of internal gettering (IG) in IC manufacturing. Gettering schemes play an important role in yield management in IC manufacturing.

LOWER RESISTIVITY DRIVES POWER SEMICONDUCTORS

As appeared in Semiconductor International, February 2001 
Adobe Acrobat ® PDF Format (55KB). Posted with permission.

The power semiconductor industry has grown at an accelerating pace since its beginning in the late 1950's. Power semiconductors are a subset of the analog semiconductor market. Analog semiconductors process signals from real world phenomena such as light, heat, and pressure, while digital semiconductors process information in binary numbers.

E-BUSINESS: THE INTERNET CLOUD'S SILVER LINING

As appeared in Semiconductor International, January 2001
Adobe Acrobat ® PDF Format (166KB). Posted with permission.

The old axiom a picture is worth a thousand words is clearly demonstrated by the cloud graphic used universally by information technologists to depict the Internet. Appropriate perhaps because for many, their understanding of the Internet is still somewhat cloudy. If that is the case, then for the semiconductor industry, the silver lining around the Internet cloud is e-business. SunEdison Semiconductor Electronic Materials, Inc. has been e-enabled sine the early 1990’s when we collaborated with a key customer to send invoices electronically, through a Value Added Network,using ANSI X12 standards.

GRANULAR POLYSILICON LEADS TO BREAKTHROUGHS IN WAFER MANUFACTURING

As appeared in Semiconductor International, November 2000 
Adobe Acrobat ® PDF Format (89KB). Posted with permission.

FLEXIBILITY. LOWER COSTS. HIGHER YIELDS. These objectives are critical to semiconductor manufacturers and silicon wafer manufacturers alike. They drive semiconductor manufacturers to demand more from silicon wafers, the base starting material for a vast majority of semiconductor devices. Likewise, silicon wafer manufacturers drive advances in the base raw material in the manufacture of silicon wafers polysilicon.

THIN EPI LAYERS SHOWN TO IMPROVE GATE OXIDE INTEGRITY PERFORMANCE

As appeared in Semiconductor International, October 2000
Adobe Acrobat ® PDF Format (27KB). Posted with permission.

It is widely accepted in the silicon industry that one of the most detrimental defects inducing Gate Oxide Integrity (GOI) failures are COPs (Crystal Originated Particles). The correlation between COPs and GOI performance in polished wafers has been confirmed and published. In the same manner, COPs have also been shown to correlate with vacancy defects, or flow pattern defects in polished wafers as well.

NEW GETTERING PROCESS INSURES HIGH YIELD

As appeared in Semiconductor International, August 2000
Adobe Acrobat ® PDF Format (69KB). Posted with permission.

The drive towards higher performing semiconductor devices continues as the demand for advanced cutting-edge technology speeds into the future. Internal gettering (IG) is the primary process used to create a defect-free near-surface region in a silicon wafer used for semiconductor fabrication.

SILICON WAFER SUPPLIERS LOOK TO TOMORROW'S DEMANDS

As appeared in Semiconductor International, July 2000
Adobe Acrobat ® PDF Format (88KB). Posted with permission.

Here's proof that we are living in exciting times. Semiconductor manufacturers keep pushing to make devices that function faster, better and cheaper so our lives can keep up with daily demands.

A History of Industry Innovation– Ultraflat Polished Silicon Wafers

Not Yet Published
Adobe Acrobat ® PDF Format (64KB)

Early Challenges for Flatter Wafers -- In the early to mid 1960s, the Department of Defense began pushing the infant semiconductor industry with a desire to replace the vacuum tubes in the Minuteman ballistic missiles with solid state integrated circuits. The impetus by the Defense Department caused an even greater interest and demand by semiconductor device makers for flatter silicon wafers. While epi technology was still in development in SunEdison Semiconductor and in the silicon industry, SunEdison Semiconductor also began to invest resources to produce ultraflat silicon wafers.