Technical Papers

COMPARISON OF SPOT AND WIDE BEAM IMPLANTERS FOR MAKING SOI WAFERS BY LAYER TRANSFER

Z. Jost, A. Jones, C. Lottes, I. Peidous, M. Ries, A. Usenko
Presented at "International Conference on Ion Implantation Technology" in Portland, Oregon, 26 June - 4 July 2014.
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The quality of silicon-on-insulator (SOI) wafers manufactured with either spot beam implanter or wide beam implanter are compared. The comparison shows similar quality wafers and a potential advantage of wide beam implanters in throughput.

depth profiles of oxygen precipitates in nitride-coated silicon wafers subjected to rapid thermal annealing

V.V. Vronkov, R. Falster, TaeHyeong Kim, SoonSung Park, T. Torack
Journal of Applied Physics, Volume 114, No. 4, (Jul 2013).
©AIP Publishing, reproduced with permission.
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Silicon wafers, coated with a silicon nitride layer and subjected to high temperature Rapid Thermal Annealing (RTA) in Ar, show-upon a subsequent two-step precipitation anneal cycle (such as 800 °C + 1000 °C)-peculiar depth profiles of oxygen precipitate densities. Some profiles are sharply peaked near the wafer surface, sometimes with a zero bulk density. Other profiles are uniform in depth. The maximum density is always the same. These profiles are well reproduced by simulations assuming that precipitation starts from a uniformly distributed small oxide plates originated from RTA step and composed of oxygen atoms and vacancies ('VO2 plates'). During the first step of the precipitation anneal, an oxide layer propagates around this core plate by a process of oxygen attachment, meaning that an oxygen-only ring-shaped plate emerges around the original plate. These rings, depending on their size, then either dissolve or grow during the second part of the anneal leading to a rich variety of density profiles.

understanding the effects of impurities and grain boundaries on mechanical behavior of si via nanoindentation of (110)/(100) direct si bonded wafers

K. Youssef, X. Yu, M. Seacrist, G. Rozgonyi
Journal of Materials Research, Volume 27, No. 1 (2012), pp 349-355
©Materials Research Society

Nanoindentation was used to examine the impact of impurities and grain boundaries on mechanical properties of a “model” (110)/(100) grain boundary (GB) interface prepared using direct-silicon-bonding (DSB) via the hybrid orientation technique of (110) and (100) p-type silicon wafers. Remarkable differences were found  between the mechanical behavior of the Fe and Cu contaminated samples. The DSB  wafers contaminated with either Fe or Cu showed opposite effects on mechanical  properties, with Fe enhancing the silicon hardness, while Cu contamination induces a  gradual weakening. High resolution transmission electron microscopy (HRTEM) has been used to verify that the abrupt hardness changes observed during increasing nanoindentation loading is attributed to local deformation induced by GB interface, Cu precipitate colony induced dislocations, as well as the abrupt crystallographic orientation change across the GB. The dislocation loop generation facilitated the deformation process during nanoindentation and therefore softened the material. 

growth of 450mm diamter semiconductor grade silicon crystals

Z. Lu, S. Kimbel
Journal of Crystal Growth, Volume 318, No. 1 (2011), pp 193-195.
©Elsevier

the impact of organic contamination on the oxide-silicon interface

D. Codegoni, M.L. Poligano, L. Castellano, G. Borionetti, F. Bonoli, A Nutsch, A. Leibold, M. Otto
Presented at "Frontiers of Characterization and Metrology for Nanoelectronics" in Grenoble, France, 23-26 May 2011.
©AIP Publishing, reproduced with permission. 
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This paper collects the results of a study aimed to investigate the impact of organic contamination on the electrical properties of the silicon oxide and of the silicon oxide-silicon interface. Some wafers were contaminated by immersion in solution of diethylphthalate (DEP) in solvent. The wafers were then oxidized to perform surface recombination velocity measurements by Elymat, and capacitors were fabricated for capacitance vs. voltage and capacitance vs time measurements. In addition, the interface state density was measured by the MOS-DLTS technique and the gate oxide integrity was evaluated by constant current stress. Elymat measurements of surface recombination velocity show that surface recombination velocity is increased by organic contamination. From the point-of-view of the intrinsic properties of the silicon oxide-silicon interface, MOS-DLTS showed the most significant effects. These measurements allowed identifying a band of interface states located around E v+0.1eV as related to organic contamination. However, the most relevant effects of organic contamination were observed by electrical stress of the oxide. Indeed, the fraction of capacitors with degraded breakdown voltage increased dramatically in contaminated wafers.

the nature of lifetime-degrading boron-oxygen centres revealed by comparison of p-type andn-type silicon

V.V. Vronkov, R. Falster, K. Bothe, B. Lim, J. Schmidt
Solid State Phenomena, Vols. 178-179 (2011), pp 139-146.
©Trans Tech Publications, reproduced with permission. Available online at www.scientific.net.
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Illumination-induced degradation of minority carrier lifetime was studied in n-type Czochralski silicon co-doped with phosphorus and boron. The recombination centre that emerges is found to be identical to the fast-stage centre (FRC) known for p-Si where it is produced at a rate proportional to the squared hole concentration, p2. Since holes in n-Si are excess carriers of a relatively low concentration, the time scale of FRC generation in n-Si is increased by several orders of magnitude. The generation kinetics is non-linear, due to the dependence of p on the concentration of FRC and this non-linearity is well reproduced by simulations. The injection level dependence of the lifetime shows that FRC exists in 3 charge states (-1, 0, +1) possessing 2 energy levels. The recombination is controlled by both levels. The proper identification of FRC is a BsO2 complex of a substitutional boron and an oxygen dimer. The nature of the major lifetime-degrading centre in n-Si is thus different from that in p-Si - where the dominant one (a slow-stage centre, SRC) was found to be BiO2 – a complex involving an interstitial boron.

niobium contamination in silicon

M.L. Poligano, D. Codegoni, G. Borionetti, F. Bonoli, J. Brivio, S. Greco, A. Marino, P. Monge, I. Patoprsta, V. Privitera, C. Riva
ECS Trans. Volume 33, No. 11 (2010), pp 133-144.
©The Electrochemical Society, reproduced with permission.
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In this paper niobium is characterized as a silicon contaminant. It is shown that niobium is a relatively slow diffuser, with an intermediate diffusivity between very slow diffusers such as molybdenum and fast diffusers such as iron. Niobium is found to be very effective as a recombination center, and in addition prone to surface segregation. In addition, niobium shows optical activation, but no thermal activation. Three deep levels arerevealed in niobium contaminated silicon, plus an additional level observed in high contamination dose samples only. One of these levels is located very close to midgap, and consistently niobium was also found very effective in degrading the generation lifetime.

DEFECT DYNAMICS IN THE PRESENCE OF NITROGEN IN GROWING CZOCHRALSKI SILICON CRYSTALS

Milind S. Kulkarni
Journal of Crystal Growth 310 (2008) 324–335
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Many crystallographic imperfections termed microdefects form in silicon crystals during their Czochralski growth. These are the aggregates of vacancies, of self-interstitials, or of oxygen (silicon dioxide). The distribution of microdefects can be strongly influenced and controlled by the addition of impurities such as nitrogen to the crystal. A model describing the Czochralski defect dynamics in the presence of nitrogen and oxygen is proposed and solved. The reactions between vacancies and self-interstitials, nitrogen monomers and dimers, nitrogen and vacancies, and the reactions involving vacancies, oxygen, and complexes of vacancies and oxygen are incorporated, along with the formation of various microdefects. All microdefects are approximated as spherical clusters. The formation of all clusters is described by the classical nucleation theory. The clusters, once formed, grow by diffusion-limited kinetics. The microdefect distributions in Czochralski crystals growing under steady state as well as unsteady state are discussed.

EPITAXIAL CVD FILM DEPOSITION FLUID-DYNAMICS SIMULATION INCORPORATING DETAILED REACTOR GEOMETRY

John A. Pitney, Srikanth Kommu
214th ECS Meeting, MA2008-02, October 12-17, 2008
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As the semiconductor industry moves to the 45nm node and beyond, the specifications for silicon wafer flatness continue to become stringent. In the case of epitaxial wafers, any non-uniformity in the thickness of the deposited film potentially can degrade the wafer flatness. While the epitaxial reactors currently employed in 300mm wafer manufacture produce films with thickness deviations of order 1% over the entire wafer surface, current and future flatness requirements demand ever-improving film thickness uniformity.

IMPACT OF THERMAL PROCESSING ON SILICON WAFER SURFACE ROUGHNESS

Larry W. Shive and Brian L. Gilmore
Journal of Electrochemical Society ECS Trans. 16 (8), 401 (2008)
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Very flat silicon wafers with nanometer scale roughness are important during semiconductor device patterning onto the wafer. Recent reports have shown that thermal processing at high temperature in H2 or H2-Ar mixtures may be used to reduce roughness of silicon wafers at short length scales such as 1- 10ìm. This paper reports the impact upon roughness of high temperature heat treatment in a diffusion furnace in mixtures of hydrogen and argon. Experiments show surface roughness is reduced during high temperature processing and is independent of argon or argonhydrogen processing environment for length scales in the range of 0.1-100µm.

Lateral incorporation of vacancies in Czochralski silicon crystals

Milind S. Kulkarni
Journal of Crystal Growth 310 (2008) 3183–3191
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Silicon crystals grown by the Czochralski process typically contain many structural imperfections termed microdefects. The formation of microdefects requires an abundance of one of the intrinsic point defect species of silicon, vacancies or self-interstitials. The distribution of microdefects in a growing Czochralski crystal is influenced by its temperature field and the boundary conditions defined by its surfaces. This paper addresses the effects of the lateral surface on the defect dynamics in a growing crystal in which both the intrinsic point defect species are in comparable and low concentrations, away from the lateral surface, at higher temperatures near the melt/crystal interface. Under such conditions, a moderate vacancy supersaturation develops in the vicinity of the lateral surface leading to the formation of oxygen clusters and small voids, at lower temperatures. The vacancy incorporation near the lateral surface is driven by an interplay among the Frenkel reaction, the diffusion of the intrinsic point defects, and their convection.

THEORETICAL ANALYSIS OF THERMALLY INDUCED STRUCTURAL DEFORMATION AND RELAXATION OF SILICON WAFER

B. Harish Kumar, Shantanu Roy, John Pitney, Tom Torack and Srikanth Kommu
Journal of Electrochemical Society ECS Trans. 16 (6), 261 (2008)
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This work is focussed on the modeling and simulation of structural deformation of silicon wafers during their initial heat-up in a CVD reactor chamber, prior to the chemical vapor deposition process. The wafer structural deformation can lead to some detrimental defects that are unacceptable for semiconductor device processing. In this work, we have developed a numerical model to simulate the wafer structural deformation as a function of some key process parameters. The main objective of this simulation work is to provide guidance on the optimal process conditions at which the wafer deformation and the resulting defects can be minimized.

A Theoretical and Experimental Study of Stresses Responsible for the SOI Wafer Warpage

S. Y. Dhumal, S. Kommu
Journal of Electrochemical Society ECS Trans. 16 (6), 57 (2008)
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Silicon-on-insulator (SOI) wafers are nowadays being prominently used for the manufacture of new generation semiconductor devices. In order to maximize the device yield, the device industry is seeking SOI wafers that meet very stringent wafer specifications such as very low wafer bow and warp. An SOI wafer can undergo severe process-induced stresses during its manufacture leading to significant wafer bow and warp. The objective of this study is to understand and control the process-induced stresses in SOI wafer in order to meet the stringent bow and warp specifications.

Defect Dynamics in the Presence of Oxygen in Growing Czochralski Silicon Crystals

Milind S. Kulkarni
Journal of Crystal Growth 303 (2007) 438–448
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Modern Czochralski (CZ) silicon crystals contain various crystallographic imperfections known as microdefects that affect the yield and the performance of microelectronic devices. These microdefects are primarily the aggregates of the intrinsic point defects of silicon, vacancies and self-interstitials, and of oxygen (silicon dioxide). The distribution of microdefects in a CZ crystal is determined by the complex dynamics influenced by various reactions involving the intrinsic point defects and oxygen, and their transport. Two-dimensional oxygen influenced transient defect dynamics in growing CZ crystals is quantified and solved. The Frenkel reaction and the reactions between vacancies and oxygen are considered. The formation of all microdefects is described by the classical nucleation theory. Microdefects are assumed to be spherical clusters that grow by a diffusion-limited kinetics. The predictions of the model agree well with experimental data. Various predictions of the model and experimental results are discussed.

The Agglomeration Dynamics of Self-interstitials in Growing Czochralski Silicon Crystals

Milind S. Kulkarni, Joseph C. Holzer, Lee W. Ferry
Journal of Crystal Growth 284 (2005) 353-368
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Silicon single crystals grown by the Czochralski process can contain various defects known as microdefects, formed by the agglomeration of vacancies and self-interstitials (or interstitials). The dynamics of the formation of interstitialtype microdefects is studied. Interstitials form globular clusters called B defects, which, upon sufficient growth, transform into the large dislocation loops known as A defects. A growing crystal exhibits a nucleation and growth zone, in which, at any given time, interstitials agglomerate to form B defects, B defects grow and transform into A defects, and A defects grow in size. The growth of the formed microdefects decreases the interstitial supersaturation and suppresses the formation of new microdefects. By suddenly decreasing the temperature of the active nucleation and growth zone, the linear sizes of the relatively larger agglomerated A defects can be frozen, and smaller B and A defects in higher densities can be formed, facilitated by a rapid increase in the interstitial supersaturation. The co-existence of both B and A defects was experimentally verified, and the width of the nucleation and growth zone was characterized. The quantification of the rapid-cooled nucleation and growth zone provides insights into the formation and the growth of the interstitial microdefects in particular and defect dynamics in general.

A SELECTIVE REVIEW OF THE QUANTIFICATION OF DEFECT DYNAMICS IN GROWING CZOCHRALSKI SILICON CRYSTALS

Milind S. Kulkarni
Ind. Eng. Chem. Res. 2005, 44, 6246-6263
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A vast majority of modern microelectronic devices are built on the monocrystalline silicon substrates produced from the crystals grown by the Czochralski (CZ) process and the float-zone (FZ) process. Silicon crystals inherently contain various precipitates known as microdefects that often affect the yield and the performance of many devices. Hence, the quantitative understanding and the control of the microdefect formation and the microdefect distributions in silicon crystals play a central role in determining the quality of silicon substrates. This paper reviews significant developments in the field of the quantification of the defect dynamics in growing CZ and FZ crystals. The breakthrough discovery of the initial point defect incorporation in the vicinity of the melt/crystal interface made in the early 1980s allowed a simplified quantification of the CZ and the FZ defect dynamics. A deeper insight into the formation and the growth of microdefects was provided over the past decade by various treatments of the agglomeration of the intrinsic point defects of silicon. In particular, a rigorous quantification of the agglomeration of the point defects using the classical nucleation theory, a recently developed lumped model that captures the microdefect distribution by representing the actual population of microdefects by an equivalent population of identical microdefects, and another rigorous treatment involving the Fokker-Planck equations are discussed in detail.

Silicon Starting Materials for Sub-65nm Technology Nodes

Mike Seacrist
SCP Symposium, June 2005
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Maintaining the pace of MOSFET device scaling has become increasingly difficult in the sub-100nm gate length regime. Increased chip functionality and device performance gains drive scaling. But, simple scaling of the channel length and gate oxide thickness is no longer sufficient to deliver the ~ 17% yearly speed / power performance enhancement target for high performance logic device technologies. Problems include short channel device effects such as sub-threshold leakage current and threshold voltage changes induced by the drain voltage (DIBL), and the high level of leakage current through the ultra-thin gate dielectric. These leakage currents cause higher static power dissipation. Active switching power is another key problem where a higher number of gates switching at high frequency with only modest reductions in supply voltage result in high active power density. The problems facing device scaling necessitate new solutions. The desired solution is one that enables continued critical dimension scaling at high yield, increases MOSFET drive current while reducing source to drain and gate leakage currents, reduces short channel effects, and reduces the active power density. The potential solution space includes changes in device fabrication materials, device architectures, and the silicon wafer starting materials. This paper will describe device problems faced for sub-65nm technology nodes. Potential silicon wafer solutions for sub-65nm technology nodes will be discussed and compared. Silicon wafer manufacturing considerations such as maintaining the core silicon wafer parametric requirements for extremely flat surfaces with low particulate, low metals, and low surface roughness will be reviewed.

Simplified Two-Dimensional Quantification of the Grown-in Microdefect Distributions in Czochralski Grown Silicon Crystals

Milind S. Kulkarni and Vladimir V. Voronkovb
Journal of The Electrochemical Society, 152 .10. G781-G786. 2005
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A computationally efficient model to quantify the microdefect distributions in Czochralski grown silicon crystals is proposed and numerically solved. All microdefects are approximated as spherical clusters. The novelty of the proposed model centers on a simplified treatment of the population of the clusters at any location; the average radius of the clusters in the population is approximated by the square root of the average of the squared radii of all clusters. The formation of the clusters is described by the classical nucleation theory. The growth of the clusters at any location is quantified by an auxiliary variable proportional to the total surface area of the clusters present at the location. A comparison between the predictions of the novel model with both a traditional model treating the size distribution of the clusters in the actual cluster population and the experimental observations validate the novel model.

DEFECT CONTROL IN SILICON CRYSTAL GROWTH AND WAFER PROCESSING

Robert Falster
Presented at "International Symposium on Processing Technology and Market Development of 300mm Si Materials" in Beijing 8-9 September 2003
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Accurate control of the defectivity of silicon crystals and wafers is a subject of immense importance to both the silicon and IC industries. Exploding costs of wafer development and production as well as the processing of 300mm wafers means that predictive defect engineering is now, more than ever a requirement for both industries. There is little scope any more for iterative approaches to these problems. It is simply too expensive. Where ever possible generic – as opposed to application specific or tailored - wafer products suitable for a wide variety of demanding applications must be developed in order meet cost targets. This paper reviews recent developments in the understanding several aspects of defect control in silicon crystal growth and wafer processing which are of particular relevance to 300mm silicon products and processes. Among the subjects covered are the problems of intrinsic point defect concentration and reaction control in the growth crystals including effects of impurities and the uses of vacancy concentration profiles installed into silicon wafer in order to achieve ideal oxygen precipitation performance. The importance of accurate modeling of defect dynamics is stressed. Finally, the requirement of dealing with significantly higher levels of mechanical stress in 300 mm processing has led to a new appreciation of the role played by oxygen in the locking of dislocations and the dynamics of wafer hardening during processing. These developments are reviewed briefly.

DYNAMICS OF POINT DEFECTS AND FORMATION OF MICRODEFECTS IN CZOCHRALSKI CRYSTAL GROWTH: MODELING, SIMULATION, AND EXPERIMENTS

Milind S.Kulkarni, V.V.Voronkov and Robert Falster
This article was first published in Future Fab International, Volume 14, February 11, 2003, published by Montgomery Research, Inc., San Francisco, CA -- reproduced with permission. 
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Most common microdefects in Czochralski silicon, voids and dislocation loops, are formed by agglomeration of point defects, vacancies and self-interstitials, respectively. Dynamics of formation and growth of the microdefects along with the entire crystal pulling process is simulated. The Frenkel reaction, the transport and the nucleation of the point defects and the growth of the microdefects are considered to occur simultaneously. The nucleation is modeled using the classical nucleation theory. The diffusion-limited growth of the nucleated precipitates is assumed. The microdefect distribution at any given location is captured on the basis of the formation history of nuclei. The microdefect type and size distributions in crystals grown under steady state as well as unsteady state are predicted. The surface energies for voids and interstitial clusters are determined using experimental results. The model predictions agree very well with the experimental results. Various predictions of the model are presented and the results are discussed.

GROWN-IN MICRODEFECTS IN SILICON AS A GUIDE TO THE PROPERTIES OF POINT DEFECTS

V.V.Voronkov and Robert Falster
This article was first published in Future Fab International, Volume 15, July 11, 2003, published by Montgomery Research, Inc., San Francisco, CA -- reproduced with permission. 
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Simulation of vacancy and self-interstitial distributions in silicon crystals is an important modern field of activity[1-3]. In order to perform such simulations, values for many parameters of the intrinsic point defects are required. There are five basic constants for the self-interstitials: two for the equilibrium concentration (the melting point value Cim and the formation energy Ei), two for the diffusivity (the melting point value Dim and the migration energy Eid) and one for the drift velocity along the temperature gradient (the drift energy εi). Also, there are five similar constants for vacancies: Cvm, Ev, Dvm, Evd and εv. The problem, in its simplest (and conventionally accepted) version – when a fast recombination of vacancies and self-interstitials is assumed – contains 10 parameters. None of them is well defined, in the current state of knowledge. If one chooses to consider a finite recombination rate, then two more parameters are required in order to describe the temperature dependence of the rate constant. We stick to the model of fast recombination, which is consistent with the V/G rule[3,4] ie, that the type of intrinsic point defect incorporated into crystal locally – near the crystal-melt interface – is controlled by the ratio of the growth rate (V) to the local temperature gradient (G). Vacancies are incorporated if V/G is greater than some critical ratio (V/G)cr and self-interstitials are incorporated at V/G <(V/G)c.

A NOVEL METHOD FOR ACHIEVING VERY LOW COPS'S IN CZ WAFERS

Jiri Vasat and Tom Torack
An edited version of this paper appeared in the March 2003 issue of Solid State Technology 
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As the IC industry moves toward development of future technology nodes and application of new materials, more innovation is required at the wafer substrate level. The silicon-on-insulator (SOI) technology will be a key factor in extending planar CMOS technologies beyond sub-50nm gate sizes. Many of the process and materials constrains facing continuous device scaling are relaxed or removed for devices fabricated on SOI wafers.

The concentration field of self-interstitials and vacancies in silicon depends on at least 10 parameters. But for the specific case of the growth of crystals deep in the interstitial mode, it is primarily sensitive to only the 3 parameters of the self-interstitial transport: the melting point diffusivity Dim, the migration energy Eid and the drift energy i. A fit for these parameters can be obtained via the shape of A-swirl regions in quenched crystals. Using this approach, the resulting value for Dim is found to be about 1.5x10-4 cm2/s (which considerably lower than a commonly assumed value) while i is about 4 to 8 eV (a surprisingly strong uphill drift). This conclusion is still tentative and subject to some uncertainty related to a possible effect of carbon.

QUANTIFICATION OF DEFECT DYNAMICS IN UNSTEADY-STATE AND STEADY-STATE CZOCHRALSKI GROWTH OF MONOCRYSTALLINE SILICON

Milind S.Kulkarni, Vladimir Voronkov and Robert Falster
An edited version of this paper appeared in the March 2003 issue of Solid State Technology 
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Most Common microdefects in Czochralski silicon, voids and dislocation loops, are formed by agglomeration of point defects, vacancies and self-interstitials, respectively. Dynamics of formation and growth of the microdefets along with the entire crystal pulling process is simulated. The Frenkel reaction, the transport and nucleation of the point defects and the growth of the microdefects are considered to occur simultaneouslu. The nucleation is modeled using the classical nucleation theory. The microdefects are approximated as spherical clusters, which grow by a diffusion-limited kinetics. The microdefect distribution at any given location is captured on the basis of the formation and path histories of the clusters.The microdefect type and size distributions in crystals grown under various steady states as well as unsteady states are predicted. The developed one-dimensional model captures the salient features of defect dynamics and reveals significant differences between the steady-state defect dynamics and unsteady-state defect dynamcis. The model prediction agree very well with the experimental observations. Various predictions of the model are presented, and results are discussed.

A Review and Unifying Analysis of Defect Decoration and Surface Polishing by Chemical Etching in Silicon Processing

Milind S. Kulkarni
Ind. Eng. Chem. Res. 2003, 42, 2558-2588
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A comprehensive review of dynamics of etching and its various applications in silicon wafer processing is accomplished, and new developments are discussed. A previously proposed pseudo two-phase phenomenological model to describe the dynamics of three-phase etching is revisited and novel augmentations are proposed. Interplay between the liquid-phase transport of reagents, the silicon surface kinetics, and the formation and the transport of gaseous bubbles is quantified. Both the model and the reported data explain effects of etching on silicon-surface polishing. Recent attempts to extend the pseudo two-phase model to describe the defect decoration by acidbased etching are discussed and new modifications are proposed. Microdefect (agglomerated defect) distribution in a monocrystalline silicon wafer is identified by growing copper precipitates on the microdefects followed by surface polishing and subsequent microdefect-decorating etching, which forms the pits on the wafer known as etch-pits by a relatively rapid chemical dissolution of the precipitates. The macrodecoration of microdefects is typically realized in the absence of significant effects of the liquid-phase mass-transport. The developed phenomenological model leads to classification of etchants as either polishing or potentially decorating and to the identification of conditions necessary for an efficient microdefect decoration. The reported analytical expressions for the microdefect-decorating and the microdefect-polishing conditions are also revisited, revised, and augmented. A series of reported experiments validates the developed model.

AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW TRENCH ISOLATION

Anthony E. Stephens
In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 774, The Electrochemical Society Proceedings Series, Pennington, NJ (2002).
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Although the silicon wafer is strong at room temperature, it is weak at the elevated temperatures necessary for the fabrication of integrated circuits. During thermal processing, a nonuniform elevated temperature produces a nonuniform expansion within the wafer and the resulting lattice forces can cause local or widespread furnace slip. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. Matters are made worse when shallow trench isolation structures are built into the wafer surface. During thermal cycling, the pressure oxide exerts on the silicon side-walls can create dislocations or cause slip-dislocations to move into the device.

THE CONTROL OF BORON AUTODOPING DURING DEVICE PROCESSING FOR P/P+ EPI WAFERS WITH NO BACK-SURFACE OXIDE SEAL

M.J. Binns, S. Kommu, M.R. Seacrist, R.W. Standley, R. Wise, and D.J. Myers of SunEdison Semiconductor. D. Tisserand, and D. Doyle of Texas Instruments, Inc.
In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 682-704, The Electrochemical Society Proceedings Series, Pennington, NJ (2002).
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Experiments have been carried out to measure the amount of boron autodoping that occurs when P/P+ wafers with no back-surface oxide seal are annealed in both pure N2 and O2 gases for various times and temperatures in a batch furnace. It is found that the near surface boron concentration, [B]NS = 9.06 x 10 27 exp (-3.25eV/kT) cm -3 in the temperature range 1050¡C-1200¡C and is largely independent of time in the range 2-8 hours. Autodoping is highest at the wafer center and decreases toward the edge. The critical oxide thickness on the wafer front surface needed to prevent autodoping is 600?. No boron autodoping could be detected for any anneals in O2 gas. Boron autodoping due to outgassing of furnace components can be prevented by avoiding any high temperature heat-treatments of P/P+ wafers with no back oxide (LTO) layer in pure nitrogen gas, or by ensuring that the front surface of the wafers always have an oxide layer greater than the critical thickness (600?). In addition, boron autodoping during epitaxy for both 200mm and 300mm P/P+ wafers can be controlled using a modification to the epi hardware/process.

*The posting of this technical paper to the SunEdison Semiconductor web site does not imply support for any SunEdison Semiconductor products(s) or service(s) by Texas Instruments. This paper was a result of joint research by the engineering staffs of SunEdison Semiconductor Electronic Materials, Inc., and Texas Instruments. Printed with permission of Texas Instruments.

DETERMINATION OF MINIMUM OXYGEN PRECIPITATION GROWTH CONDITIONS FOR GETTERING OF COPPER AND NICKEL, PV 2002-2, P.638

M. Seacrist, M. Stinson, J. Libbert, R. Standley, and J. Binns
Semiconductor Silicon 2002 (9th International Symposium), H. R. Huff, L. Fabry, and S. Kishino, Editors, The Electrochemical Society Proceedings Volume Series, PV 2002-2, The Electrochemical Society, Inc., Pennington, NJ (2002)
©The Electrochemical Society, Inc., reproduced with permission 
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Advanced device technologies have reduced thermal process temperatures and times as compared with prior device generations. A key consideration for internal gettering (IG) using oxygen precipitates has become the minimum thermal conditions under which the oxygen precipitates grow large enough in size to become effective gettering sites. These experiments determine the minimum oxygen precipitate growth conditions necessary in MDZ® wafers to getter very high levels of Cu and Ni contamination intentionally introduced at the sample backsurface and then diffused into the wafer.

EFFECTIVE INTRINSIC GETTERING FOR 200MM AND 300MM P/P-WAFERS IN A LOW THERMAL BUDGET 0.13ΜM ADVANCED CMOS LOGIC PROCESS

M.J. Binns, S. Bertolini, R. Wise, D.J. Myers and T.A. McKenna of Texas Instruments, Inc.
In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 647-657, The Electrochemical Society Proceedings Series, Pennington, NJ (2002).
©The Electrochemical Society, Inc., reproduced with permission
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200mm and 300mm P/P- epitaxial wafers with and without an MDZ® (Magic Denuded Zone) heat-treatment have been processed through a low thermal budget 0.13 µm advanced CMOS Logic process. Measurements at key stages in the process show that very little precipitation (below detection limit) occurs in the standard P/P- wafers. In contrast, very uniform precipitation with consistent BMD (bulk micro-defect) and PFZ (precipitate-free zones) are observed for both 200mm and 300mm P/P-wafers that received the prior MDZ® heat-treatment. This was demonstrated by subjecting the wafers to an additional 16 hour 1000 ¡C anneal designed to grow precipitates to a size where they become detectable by the cleave and etch technique. In addition, nickel haze gettering tests clearly demonstrated that reliable gettering of nickel (up to 1x10 14 cm -2 ) can be obtained early in the device process for wafers which received the MDZ® heat-treatment without the need for the additional 16 hour 1000 ¡C anneal. However, nickel haze was observed for standard P/P- epitaxial wafers even at the end of the process indicating the complete lack of any intrinsic gettering.

*The posting of this technical paper to the SunEdison Semiconductor web site does not imply support for any SunEdison Semiconductor products(s) or service(s) by Texas Instruments. This paper was a result of joint research by the engineering staffs of SunEdison Semiconductor Electronic Materials, Inc., and Texas Instruments. Printed with permission of Texas Instruments.

EFFECTIVE INTRINSIC GETTERING OF COPPER DURING A SUB-QUARTER MICRON CMOS PROCESS

Ki-Man Bae, Jong-Rock Kim, Young-Ki Hong, Sung-Il So, Sung-Chul Lee, Sung-Su Kim, Sang-Woon Ha, Chung-Geun Koh, Seung-Ho Pyi,and Dong-Myun Lee
Semiconductor Silicon 2002, H.R. Huff, L. Fabry and S,Kishino, Editors PV 2002-02, p.786
©The Electrochemical Society, Inc., Pennington, NJ (2002), reproduced with permission
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An IG solution for gettering of copper was studied in conjunction with a fibrous defect that lowered the yield of a sub-quarter micron DRAM. A high density of fibrous defects distributed in a ring pattern was found after the polysilicon gate process of an advanced DRAM. In optical microscopy after Secco etching, the formation of the fibrous defect was correlated with S-pits. From the cleaved cross-sectional analysis, the defective wafer had a very low density of BMDs, while the good wafer had a high density of BMDs. From these results, the fibrous defect was caused by copper precipitation as a result of the lack of IG. The ring-pattern distribution of the fibrous defect was explained with respect to the inhomogeneous radial distribution of grown-in BMD nuclei, a characteristic of the vacancy-interstitial mixed type crystal. In the intentional contamination with copper followed by a DRAM thermal simulation, the MDZ treated sample resulted in complete gettering, as evidenced by no haze formation on the surface. This demonstrates the effectiveness of MDZ as a reliable IG solution for advanced CMOS processes.

EXPERIMENTAL METHOD TO DETERMINE AN ACCEPTABLE CONCENTRATION OF IRON IMPURITY IN HOT ZONE STRUCTURAL COMPONENTS

H.Sreedharamurthy, Mike Seacrist, John Holder, Mohsen Banan
In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 774, The Electrochemical Society Proceedings Series, Pennington, NJ (2002).
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A measurement method has been developed to analyze iron present in the hot zone structural components. In this method, the samples are heated to temperatures of 800 C, 950 C and 1100 C at atmospheric pressure of argon gas ambient, for two hours. A monitor wafter is exposed to gases generated from these heated samples. After heat treatement, the wafers are tested using a surface photovoltage measurement system for iron concentrations. The iron concentrations of the wafer are directly dependent on the iron concentrations of the samples used and thus iron present in the samples is measured indirectly. This method is capable of detecting iron outgassing from hot zone materials into silicon samples in concentrations to about 1E10atoms/cc. This test is used on a regular basis to monitor the iron levels and qualify new materials and as a tool to decide whether they are acceptable for use as a hot zone structural component.

INTERNAL GETTERING IN SILICON: EXPERIMENTAL AND THEORETICAL STUDIES BASED ON FAST AND SLOW DIFFUSING METALS

Dr. Gabriella Borionetti
Solid State Phenomena vols. 82-84 (2002). Posted with permission. 
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An in depth evaluation of internal gettering effectiveness in Si wafers has been run based on iron and nickel intentional contamination followed by minority carrier recombination centers measurements. The paper demonstrates the relevance of oxygen clusters density and stability as well as thermal treatment cooling phase conditions on gettering mechanism activation. A theoretical model is proposed taking into account both homogeneous and heterogeneous nucleation of metals at oxygen clusters and surface sites.

INTRINSIC POINT DEFECTS AND IMPURITIES IN SILICON CRYSTAL GROWTH

Dr. Robert Falster and V. V. Voronkov
Journal of the Electrochemical Society, Volume 149, No. 3, pp G167-G174 (2002). ©The Electrochemical Society, Inc., reproduced with permission  Adobe Acrobat® PDF Format (143KB)

The incorporation of intrinsic point defects into a growing crystal is affected by the presence of impurities that can react with vacancies and self-interstitials. The critical value of the ratio of the growth rate, V, to the axial temperature gradient, G, (V/ G ratio) that separates the interstitial growth mode from the vacancy growth mode, is shifted by impurities, and this effect can be described by simple analytical expressions. Some impurities, such as oxygen, nitrogen, and hydrogen, trap vacancies and cause a downward shift in the critical V/ G ratio (and also a fast increase in the fraction of trapped vacancies, on lowering T). Other impurities, like carbon, trap self-interstitials, and cause an upward shift in the critical V/ G ratio (and also an increase in the fraction of impurity interstitials, on lowering T). The impurities affect both the incorporation and agglomeration stages of micro-defect production.

ORTHOGONAL DEFECT SOLUTIONS FOR SILICON WAFERS: MDZ AND MICRO-DEFECT FREE CRYSTAL GROWTH

Dr. Robert Falster
Future Fab International, Issue 12, 240, (2002
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Defect issues such as the control of oxygen precipitation and intrinsic point defect related micro-defects have been at the centre of silicon technology for many years. These are very difficult and complex problems from both a scientific and an engineering point of view. As we now know these two problems are, importantly, highly coupled problems. Because of the complexity inherent in these problems, more often than not solutions to issues presented by such problems have produced rather highly tuned measures specific to certain applications. There are many problems associated with such highly engineered and specific wafer solutions. This paper discusses two new classes of solution to the problem of defectivity silicon wafers: the Magic Denuded Zone ® (MDZ ®) and micro-defect-free - or "perfect" crystal growth. These solutions completely break the coupling of wafer defect performance to crystal growth and application and result in clear specifications for defectivity. These solutions are not only ideal from the standpoint of the specific problem of the control and specification of oxygen behavior and microdefect performance but result in several new degrees of freedom which ultimately simplifies the specification, manufacture and use of silicon in all applications.

THE REALIZATION OF UNIFORM AND RELIABLE INTRINSIC GETTERING IN 200MM P- AND P/P- WAFERS FOR A LOW THERMAL BUDGET 0.18ΜM ADVANCED CMOS LOGIC PROCESS

Dr. Jeff Binns
Solid State Phenomena vols. 82-84 (2002). Posted with permission. 
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P- polished and P/P- epitaxial wafers with and without an MDZ® (Magic Denuded Zone) heat-treatment have been processed through a low thermal budget 0.18µm advanced CMOS Logic process. Measurements at key stages in the process clearly demonstrate that very little precipitation (below detection limit) occurs in the standard P- or P/P-wafers. In contrast, very uniform precipitation with consistent BMD (bulk micro-defect) and PFZ (precipitate-free zones) are observed for wafers that received the prior MDZ® heat-treatment. This was demonstrated by subjecting the wafers to an additional 16 hour 1000¡C anneal designed to grow precipitates to a size where they become detectable by the cleave and etch technique. In addition, nickel haze gettering tests clearly demonstrated that reliable gettering of nickel (up to 4x1016 cm-2 ) could be obtained early in the device process for wafers which received the MDZ® heat-treatment without the need for the additional 16 hour 1000¡C anneal However, nickel haze was observed for standard P-polished and P/P- epitaxial wafers even at the end of the process indicating the complete lack of any intrinsic gettering.

SILICON EPITAXY AND PARTICLE DYNAMICS: A THEORETICAL AND EXPERIMENTAL STUDY

Srikanth Kommu
In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 774, The Electrochemical Society Proceedings Series, Pennington, NJ (2002).
©The Electrochemical Society, Inc., reproduced with permission 
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The modern microelectronics industry has imposed severe demands on the quality of films produced by the silicon epitaxy process and the epitaxial film deposition techniques need to fulfill general requirements such as high growth rate, good thickness uniformity across a wafer, minimum particulate generation and economic use of reactants. In this study, robust simulation models have been developed which can provide insights for meeting the above requirements.

A TECHNIQUE FOR DELINEATING DEFECTS IN SILICON

Dr. Lucio Mule'stagno
Solid State Phenomena vols. 82-84 (2002). Posted with permission. 
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A decoration and etching technique was developed to delineate several types of defects in silicon wafers, slugs and slabs. The technique was originally developed to detect interstitial type (A) defects but it has proved highly effective in decorating all kinds of other defects. Being fast, and requiring no special equipment except an inexpensive muffle furnace and a dedicated etch bench the technique has quickly become an integral part of our characterization portfolio. We discuss below how we have used this technique and its advantages over other methods used to detect A-defects.

A THEORETICAL AND EXPERIMENTAL ANALYSIS OF MACRODECORATION OF DEFECTS IN MONOCRYSTALLINE SILICON

Milind S. Kulkarni, Jeffrey Libbert, Steven Keltner, and Luciano Mule' stagno
Journal of The Electrochemical Society, Volume 149, No. 2, pp. G153-G165 (February 2002), ©The Electrochemical Society, Inc., Pennington, NJ (2002), reproduced with permission
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Microdefect distribution in a monocrystalline silicon wafer is identified by saturating the wafer with copper at a high temperature followed by copper precipitate growth through rapid cooling followed by surface polishing and subsequent microdefect-decorating etching.

The Electrochemical Society Interface - Summer 2002 - Cover Page The Electrochemical Society Interface - Summer 2002 - Technical Highlights

EFFECTS OF DISLOCATION AND BULK MICRO DEFECTS ON DEVICE LEAKAGE

Dr. Garth K. Su, Dr. Y. H. Chen and Dr. Anthony E. Stephens
SEMICON Taiwan 2001. Posted with permission. 
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A fabricated wafer was found to show leakage near the edge of the wafer. After device stripping and decorative etching, a dislocation pattern was observed near the edge of the wafer close to the device edges. This suggests the presence of furnace stress and device fabrication stress. In addition, these dislocations were found on the good and bad devices indicating a weak dependence of device leakage on dislocations. A separate BMD analysis showed that the lack of intrinsic gettering due to low BMD density could be an additional factor for the failure mechanism. An ideal precipitation for gettering using the control of vacancy concentration profiles is proposed.

GETTERING IN SILICON: FUNDAMENTALS AND RECENT ADVANCES

Dr. Robert Falster
Semiconductor Fabtech 13th edition. Posted with permission. ©2001 
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The management of metal contamination is one of the most important aspects of successful integrated circuit manufacture. Gettering has long been an important part of this. Put simply, gettering is a stand-by process whereby metal contamination is rendered harmless in the event of a failure of process contamination control. The bones of these processes are built into silicon wafers with variable degrees of success. This article covers some of the fundamental principles that underlie this very important technology and discusses various approaches to the problem, highlighting the issues associated with each of them. Finally a new type of wafer, one which is programmed for optimal gettering, the Magic Denuded Zone (MDZ) wafer is introduced.

INVESTIGATING THE FORMATION OF TIME-DEPENDENT HAZE ON STORED WAFERS

Dr. Larry W. Shive, Dr. Richard Blank and Karen Lamb
March 2001 Issue of Micro Magazine. © Canon Communications 2001. Posted with permission. 
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The storage life of bare silicon wafers has been historically defined as the elapsed time after packaging before small particles begin to form on the surface. Many silicon wafer users have observed this time-dependent haze formation on wafers that have seen extended storage. We have investigated the surface changes of silicon wafers during 6 months and 18 months of storage and show that although most wafers have a very high potential for surface degradation, strict control of moisture inside the wafer package is the primary key to 18-month storage life. We show that surface organics, ions, oxide thickness, metals and particles remain very stable in a well-controlled package environment. However, we also show that the typical levels of organics and ions that are present on commercially available silicon wafers have the potential to form over one million particles >0.12um diameter if the wrong storage conditions exist. A general mechanism for tdh formation is proposed.

Acid-Based Etching of Silicon Wafers: Mass-Transfer and Kinetic Effects

Milind S.Kulkarni and Henry F.Erk
Journal of the Electrochemical Society, 147, (1) 176-188 (2000)
©The Electrochemical Society, Inc. reproduced with permission
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A study to understand the transport and kinetic effects in three-phase, acid-based wet etching of silicon has been accomplished. Reactants overcome the liquid-phase mass transfer resistance and the kinetic resistance to complete the reaction. The gaseous bubbles formed by the reaction adhere to random sites on the surface and, thus, mask a fraction of the surface from the reactants. This bubble masking effect is modeled as the bubble transport resistance that acts in parallel with the liquid-phase mass-transfer resistance. These transport effects are lumped into an effective mass-transport resistance, which acts in series with the kinetic resistance. It is shown that the etched surface morphology is a function of the ratio of the effective mass-transport resistance to the kinetic resistance. A rough surface is a field of peaks and valleys. It is theorized that under mass-transfer influence, etch rates at peaks are higher than etch rates at valleys. Hence, the surface is chemically polished. It is shown that the polishing efficiency increases with increasing ratio of mass-transfer resistance to the kinetic resistance, reaches a maximum, and then decreases. Effects of mass-transfer and kinetics on the surface roughness and gloss are explained by both the developed phenomenological model and experimental data.

Intrinsic Point Defects and Their Control in Silicon Crystal Growth and Wafer Processing

Dr. Robert Falster and V. V. Voronkov
MRS Bulletin, Volume 25, No. 6, pp 28-32 (June 2000)©Materials Resarch Society. Posted with permission. 
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Silicon produced for the microelectronics industry is far and away the purest and most perfect crystalline material manufactured today. It is fabricated routinely and in very large volumes. Many of the advances in integrated-circuit (IC) manufacturing achieved in recent years would not have been possible without parallel advances in silicon-crystal quality and defect engineering.

On the Properties of the Intrinsic Point Defects in Silicon: A Perspective from Crystal Growth and Wafer Processing

R Falster, VV Voronkov and F Quast
phys. stat. sol. (b), 222, 219 (2000)
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Taking into account a wide variety of recent results from studies of silicon crystal growth and high temperature wafer heat treatments, a consistent picture of intrinsic point defect behavior is produced. The relevant point defect parameters: diffusivities, equilibrium concentrations and the details of the interaction of vacancies with oxygen are deduced. This set of parameters successfully explains a very wide array of experimental observations covering the temperature range 900-1410 ¡C. These experimental observations, which are reviewed here, include the properties of grown-in microdefects and vacancy-controlled oxygen precipitation effects in rapidly cooled wafers. The analysis of point defect behavior from observations of high temperature phenomena such as these has the great advantage of relative simplicity and transparency.