PRODUCTS

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Wafer Solutions

GlobalWafers is a global leader in the manufacture and sale of wafers and related products to the semiconductor industry. Wafers are the foundation upon which virtually all of the world’s integrated circuits are built. Those products, in turn, are the building blocks for the $1 trillion electronics market (cell phones, computers, PDAs, CD/DVD players, satellite and automotive electronics, etc.). GlobalWafers has been a pioneer in the design and development of wafer technologies since 1959, and operates facilities in the U.S., Europe and Asia Pacific.

GlobalWafers can provide both standard and customized silicon wafers to meet your needs.

Analog/Discrete

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the ntire lateral and vertical region between the wfer front and back sides.
S - Surface; the surface region of a silicon wafer (usually refers to top 10μ)
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturer's line.

Processor/CMOS Logic

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the entire lateral and vertical region between the wafer front and back sides.
S - Surface; the surface regions of a silicon wafer (usually refers to the top 10μ).
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufacturer's line.

Memory

The tables below are designed to provide you with a quick-reference guide to potential silicon wafer solutions to specific device applications. Common segment drivers and problems are identified and characterized by bulk, surface, or integration issues. Solutions to problems are recommended and a quantitative and qualitative benefit analysis is provided.

B - Bulk; this refers to the entire lateral and vertical region between the wafer front and back sides.
S - Surface; the surface region of a silicon wafer (usually refers to top 10μ).
I - Integration; the degree of ease in which the silicon wafer can be integrated into the device manufaturer's line.

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Polished

Standard Wafer

Our principal product is the prime polished wafer: a highly refined, ultrapure wafer of crystalline silicon with ultraflat and ultraclean surfaces, that is custom built to meet customer specifications. Sophisticated chemical-mechanical polishing (CMP) processes remove surface defects and produce extremely flat, mirror-like surfaces. The CMP process was pioneered by GlobalWafers in 1962 and is still the industry standard today. Prime Polished silicon wafers are used in broad range of advanced integrated circuit applications by our customers.

Epi

Perfect Silicon

Perfect Silicon™ brand wafers utilize GlobalWafers' proprietary defect-free crystal growth process designed to completely suppress the formation of low-density, grown-in defects. The main principle behind the CZ single-crystal growing process lies in the rapid transport of growth-incorporated excess intrinsic point defects to harmless sinks before they have a chance to react to form defects. This method of growing CZ single-crystal controls the point defect level such that there is no excess concentration above thermodynamic equilibrium, thereby preventing clustering as the crystal cools. Such material is said to be grown under unique, dynamic quasi-equilibrium conditions. The as-grown crystal is completely defect-free, and therefore, requires no post-growth engineering, such as annealing or epitaxy.

This leads to a very homogenous silicon wafer with zero defects. Perfect Silicon brand wafers are the most advanced silicon materials available in the world today:

  • free of agglomerated defects across and throughout the whole wafer thickness.
  • 100% free of COP, D-defect, I-defect, etc.
  • no need for post-growth engineering such as annealing or epitaxy.
  • robust internal gettering and PFZ provided by patented MDZ® treatment if required by customer.

Magic Denuded Zone

Magic Denuded Zone® (MDZ®) is a patented, rapid method of achieving reproducible and reliable internal gettering in silicon wafers. It is a Rapid Thermal Process (RTP) based technique in which the oxygen precipitation behavior is controlled by the manipulation of vacancy rather than oxygen concentration profiles. GlobalWafers has engineered the RTP process to create a vacancy concentration depth profile that effectively preprograms the precipitate-free zone depth and precipitate density of the wafer to ideal targets. MDZ® produces a silicon wafer with ideal oxygen precipitation behavior, and reproducible and reliable IG which is nearly independent of the initial oxygen concentration, the thermal history effects from crystal growth, and the IC fab process application.

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Magic Denuded Zone®, MDZ®, and the MDZ® logo are registered trademarks of GlobalWafers Inc. All rights reserved.

The MDZ® process is protected by the following patents:5,994,761; 6,180,220; 6,204,152; 6,306,733; 6,586,068; 6,849,119; 6,336,968; 6,432,197; 6,709,511; 6,191,010; 6,579,779; 6,713,370.

MDZ® Literature & Other

MDZ Detailed Information

SOI

Silicon-On-Insulator (SOI) is a new type of starting material for the chipmaking process. SOI wafers have three layers; a thin surface layer of silicon (from a few hundred Angstrom to several microns thick) where the transistors are formed, an underlying layer of insulating material on a support or "handle" bulk silicon wafer. The insulating layer, usually made of silicon dioxide, is referred to as the "buried oxide" or "BOX", and is usually a few thousand Angstroms thick. Transistors built within the top silicon layer, switch signals faster, run at lower voltages, and are much less vulnerable to signal noise from background cosmic ray particles. Each transistor is isolated from its neighbor by a complete layer of silicon dioxide. These transistors are immune to "latch-up" problems and can be spaced closer together than transistors built on bulk silicon wafers. Building circuits on SOI increases Fab productivity by allowing for more compact circuit designs, yielding more chips per wafer.

SOI enables increased chip functionality without the cost of major Fab process equipment changes. Faster circuit operation and lower operating voltages have produced a powerful surge in the performance of high-speed network servers and new designs for hand-held computing and communication devices with longer battery life. Advanced circuits, using multiple layers of SOI-type device silicon, can lead the way to a coupling of electrical and optical signal processing into a single chip resulting in a dramatic broadening of communication bandwidth and new applications such as global-ranging, direct-link entertainment and communication to hand-held devices.

High Resistivity Wafers

Why Higher Resistivity Wafers?

Normal silicon wafer substrate resistivity ranges for CMOS technologies have typically spanned from a low of about 5 mohm-cm on heavily doped epi substrates to a high of around 30 ohm-cm on polished wafers. Although heavily doped substrates have proven useful for protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing in the emerging area of CMOS integration of radio frequency transceiver devices operating in the GHz frequency range.

Wireless chip designs can benefit significantly from higher substrate resistivity levels. Improvements in the performance of passive components, such as inductors, and substrate electrical isolation between the integrated digital, RF (radio frequency), and analog components are possible with higher resistivity silicon substrates Substrate resistivities greater than 40 ohm-cm are required now and in some cases resistivities in excess of 1000 ohm-cm will be needed.

High Resistivity Wafer Requirements

Key characteristics of a high resistivity or ultra-high resistivity silicon wafer are 1) a uniform resistivity through the thickness of the wafer, 2) acceptable radial and axial resistivity gradients, and 3) a resistivity that remains stable throughout device processing. These characteristics are dependent on crystal growth and the control of oxygen behavior.

To support RF-CMOS process technologies scaled to the 0.1um design rule and smaller, wafers must be available in large diameter sizes like 200mm and 300mm, and must support all the advanced wafer parametrics such as site flatness and nanotopography. Wafers must also be available in a COP-free form to achieve a very low wafer defect density for high yielding, highly integrated devices (COP is vacancy agglomerated defect from crystal growth that intersects final wafer surface). The additional capability for metallic gettering protection via oxygen precipitates is also desirable. CZ products such as Optia (COP-free polished wafer enhanced with MDZ), Aegis (P/P- epi wafer enhanced with MDZ), or Ar-Annealed wafers are best positioned to satisfy all these requirements for the case of high resistivity wafers up to 100ohm-cm. High resistivity wafers up to 100 ohm-cm are currently used in RF applications and satisfy the current performance requirements.

As wireless standards move to even higher GHz range frequencies, ultra-high resistivity wafers will be needed in order to maintain acceptable inductor quality factors and to minimize cross-talk between transistors. It's expected that the ultra-high resistivity requirement will emerge in the 2004-2005 timeframe. Ultra-high resistivity wafers into the 1000 ohm-cm range pose some additional challenges for CZ wafers that will be discussed in the next sections.

Ultra High Resistivity Wafers

Why Higher Resistivity Wafers?

Normal silicon wafer substrate resistivity ranges for CMOS technologies have typically spanned from a low of about 5 mohm-cm on heavily doped epi substrates to a high of around 30 ohm-cm on polished wafers. Although heavily doped substrates have proven useful for protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing in the emerging area of CMOS integration of radio frequency transceiver devices operating in the GHz frequency range.

Wireless chip designs can benefit significantly from higher substrate resistivity levels. Improvements in the performance of passive components, such as inductors, and substrate electrical isolation between the integrated digital, RF (radio frequency), and analog components are possible with higher resistivity silicon substrates Substrate resistivities greater than 40 ohm-cm are required now and in some cases resistivities in excess of 1000 ohm-cm will be needed.

Ultra-High Resistivity Crystal Growth

Growth of CZ crystals to 100 ohm-cm with acceptable resistivity gradients is easily achieved using existing growth processes. The amount of dopant added to the crystal is simply reduced in order to target the higher resistivity range. The rest of the crystal growth process parameters, as well as final wafer product characteristics, remain unchanged.

Growth of CZ crystals to the 1000 ohm-cm range presents some additional challenges. Because the amount of background dopant has to be significantly reduced, additional emphasis must be placed on the control of dopants, such as boron and phosphorous, introduced from the raw materials and components used in the crystal puller. These materials and components include the polysilicon source, the quartz crucible, and the graphite heater. In addition, the extremely low dopant level in the melt makes control of dopant mass transfer to, and then through, the boundary layer at the melt-solid interface important for achieving acceptable radial resistivity variation. By employing high purity puller components, and by optimizing dopant flow in the melt, GlobalWafers R&D has successfully developed the capability to grow CZ crystals with maximum resistivities into the 1000 ohm-cm range using existing 200/300mm crystal pulling equipment. Accurate and reproducible measurements of these ultra-high resistivities is also a challenge that must be addressed but will not be discussed in detail here.

Excess Silicon

GlobalWafers produces the highest quality Semiconductor grade Silicon ingots and Silicon wafers. We drive innovation and strict quality control at every step of the value chain to ensure maximum quality and consistency. Due to our high volume manufacturing, GlobalWafers generates excess silicon materials, which companies can use for a variety of applications. This high quality material can provide companies with cost effective solutions while enjoying the benefits of using good quality material in their manufacturing process. CLICK HERE to view our overview brochure.