What is gettering and how does MDZ® help?

The management of metal contamination is one of the most important aspects of successful integrated circuit manufacture. Gettering has long been an important part of this. Put simply, gettering is a stand-by process whereby metal contamination is rendered harmless in the event of a failure of process contamination control. The bones of these processes are built into silicon wafers with variable degrees of success.

Gettering fundamentals

The most important metal contaminants in silicon are iron, nickel and copper, with copper being perhaps the most dangerous of all. We will illustrate both the main problems with metals and the mechanisms that lie behind the main gettering effect using copper as our example. The behavior of a metal like copper in silicon can easily be imagined by drawing a comparison to our common experience with gases dissolved in liquids. Carbon dioxide in beer, for instance. Copper diffusion in solid silicon in fact has much in common with diffusion in liquids; it is extremely fast and it’s diffusivity is not strongly temperature dependent (at least until at or below room temperature). Copper has a rather high solubility at typical process temperatures. Silicon can soak up quite a bit of the stuff when hot. This means that any copper in contact with the wafer surface (originating, for instance, from an improperly cleaned surface or diffusion boat) is rapidly dissolved and uniformly distributed into the wafer at high temperature – within seconds at 1000 degrees C for example. (It’s important to remember that at low temperatures -- in spite of its high mobility -- copper will not appreciably dissolve into silicon. It is constrained by a low solubility –- there are however exceptions: CMP under certain conditions for example). But back to high temperature copper solutions. Upon cooling -- and this is the important point -- the solubility of copper in silicon drops rapidly. Depending upon the amount of copper actually dissolved in the silicon wafer, at some point (that is to say at some temperature) during the cooling of the wafer a copper solution will become supersaturated and progressively more so upon further cooling. At some point we get so far from equilibrium that copper precipitates out of solution and the system relaxes toward equilibrium. The form that these precipitates take is that of a copper silicide: Cu3Si. These are very damaging things.

To get a feel for what is happening in a silicon wafer at this point, consider our beer analogy. A closed pressurized bottle contains a certain concentration of carbon dioxide (the silicon wafer with a copper solution at high temperature). Opening the bottle releases the pressure, and the carbon dioxide solution -- which was perfectly happy at high pressure -- becomes rapidly supersaturated under the new, lower pressure, conditions (the copper contaminated silicon wafer during cooling). In our bottle, in what seems no time at all after flipping the lid, bubbles form (copper precipitates). But anyone who has ever looked at a beer bottle, or the glass into which the beer was poured, knows perfectly well that the bubbles don’t form just anywhere. They form at the surface of the glass. The ones present in the liquid have merely been released from the glass surface and float to the top – this is where solids and liquids part company. The reason for the location of the bubble formation is because the formation of bubbles at the glass surface is easier (requires less energy or driving force) that in the uniform liquid. Broadly speaking this is called heterogeneous precipitation. Rain happens this way. And the same thing happens to copper in silicon.

Figure 1    

An illustration of the phenomenon of surface precipitation of copper in the absence of effective gettering. Here a half-wafer has been contaminated with copper and then heated to 900 degrees C and cooled. After the heat treatment, the bottom half (below the bright line) was then angle etched with a non-defect delineating etch to an average depth of only about 2.5 microns below the surface. Then the entire sample was then defect etched to reveal copper silicide precipitates. These are found only in the upper half of the sample (seen here in (a) as a "haze" resulting from light scattering off a very high density of etch pits). In the lower half, the surface precipitates where etched away prior to the defect delineation. (b) shows illustrative micrographs of the etch pit structure in the two halves.

Assume for the moment that we have a perfect, crystalline silicon wafer who’s only defects happen to be that the perfect crystal is truncated by two flat, parallel surfaces and that it contains a certain concentration of copper at high temperature. Upon cooling this system we will reach a temperature (typically about 300-500 degrees C, depending on the copper concentration – the wafers are out of the furnace at this point!) when the dissolved copper can no longer be held in solution. Just like in our beer glass, precipitates form very, very rapidly, even explosively, on the wafer surfaces equally -- and nowhere else. This happens to be a very unfortunate fact for integrated circuit technology. One of these vulnerable surfaces is of course where the entire investment in the processed wafer lies. The precipitation of copper in silicon is a catastrophic event. Cu3Si precipitates create enormous stresses in the silicon, generating dislocations which can extend far beyond the precipitate itself, generally creating havoc in a localized area. All manner of device failure can occur.

Figure 2

TEM micrographs illustrating the kind of mess a surface copper and nickel precipitation events can make.

But there’s an upside to all of this, or rather, an advantage can be taken of what’s going on here. As we have seen in the example above, a free silicon surface is a more preferable site for metal precipitation than a perfect bulk. (A free surface contains atomic steps and there is an entire half space in which the precipitate growth is unconstrained by the crystal lattice). This differential in barriers to precipitation has important consequences for the final spatial distribution of the precipitates in a wafer -- just as in the beer glass. By preferential in the silicon wafer case, what we really mean is that a precipitation event can happen at a higher temperature, in other words before some other precipitation event could happen; less under-cooling is required to drive the reaction. Now, in such a rapidly diffusing system as copper (or nickel) in silicon, this means that, in practically no time at all (on the order of seconds, really), once the nucleation of the metal precipitates begins (at the wafer surface in this example) the growing surface-nucleated precipitates consume essentially all of the dissolved metal in the wafer. This means that there is no chance for metal to precipitate anywhere else. In effect, precipitation has been suppressed everywhere but at the preferential sites. Harnessing this preferential precipitation and the associated location-specific suppression of precipitation in an appropriate way is the essence of most practical gettering systems.

So now if, for whatever reason, process controls have failed and metal has been introduced into a silicon wafer our goal is to insure that the precipitation of that metal at the sensitive front surfaces is robustly and reliably prevented. This is the main job of gettering. Much has been written about gettering in the last 25 years or so, but in essence it all boils down to this. Now we’ve already seen that a normal surface is itself a preferential site for precipitation. It follows from the above argument that all we have to do to suppress precipitation there is to create a condition in the wafer -- somewhere other than at the wafer front surface -- which is more preferable. That is, we must create sites at appropriate locations in the wafer where the barrier to metal precipitation is still lower than that of the already low barrier free surface. This is easy.

So that’s all there is to it. Well, almost. Now, just because metal has precipitated somewhere following a heat treatment doesn’t mean that it will stay there. Metal silicide precipitates are not stable at high temperatures. Although we won’t return to this point in this brief discussion, it’s worth keeping in mind here that each time the wafer is reheated they dissolve and the whole procedure begins anew [1,2]. Gettering is a dynamic process.

Practical gettering systems: external systems

A simple way to lower the barrier to metal precipitation at a free surface is to create disorder of nearly any kind in it. If this is applied to the back surface of the wafer only then a differential between the front and back surface is achieved which alters the balance in the metal precipitation preferences between the two surfaces. Over the past 30 years or so many different back surface disordering processes have been applied to silicon wafers to achieve preferential metal precipitation at the back surface and thus effective suppression of precipitation at the front surface. Since the metal is precipitated at the back surface rather than in the bulk of the wafer (see below) such systems are called external gettering (EG) systems. Almost any kind of damage to the wafer back surface will achieve this result. The first external gettering system used in large volumes was a backside damage achieved by abrading the surface with sandpaper – an almost unbelievably crude method from today’s perspective. Refinements to this over the years included laser damage, sand blasting and a more politically correct (from an IC processing point of view) CVD deposition of a highly disordered poly-silicon film applied to the backside. Backside ion-implantation damage has also been used. Several of these techniques are still in use today and to great advantage. But there are several disadvantages to these external gettering approaches which will no doubt limit or eliminate their applicability in advanced IC applications. The first requirement is that damage applied to wafer back-surfaces should live throughout the entire IC process. This is not necessarily a given. In addition to this, the disordering processes should themselves be device defect neutral. This is also not necessarily to be taken for granted. The sand-blasting of silicon surfaces is known to create particle-generating sources which can result in the transfer of particles from the back side of silicon wafers to the front side of adjacent wafers in a diffusion boat, thus in some cases causing more damage than it sought to prevent. Poly-silicon backside coatings can be oxidized away and are certainly not applicable in future double-side polished wafers.

Practical gettering systems: internal systems

Essentially all silicon wafers for IC applications are grown by the Czochralski (CZ) method. An important difference between this method and the Floating Zone (FZ) method is that the silicon melt is contained in a quartz crucible. The main result of this is that oxygen from the crucible is unavoidably dissolved into the molten silicon and incorporated in the solid crystal ingot in rather high concentrations. For a variety of reasons, the rather low mobility of oxygen in silicon being one, this excess oxygen can precipitate homogeneously, that is, at arbitrary sites, in a silicon crystal. This can occur during the cooling of the crystal during growth and in subsequent wafer heat treatments during use. Oxygen precipitates in bulk, or interior, of silicon wafers create disorder which can effectively lower the barrier for the subsequent precipitation of metals just like disorder on the wafer surface. The potential for using bulk oxygen precipitates as a gettering mechanism was first proposed in 1977 [3] although the mechanisms were not clear at the time. In fact, it is known [4] that even very tiny oxygen precipitates at very early stages of growth (too small to observe by the conventional etching techniques normally used to see them) can result in energy barriers lower than that of a free surface and thus offer the potential for very effective suppression of surface precipitation and thus gettering. On the surface of things, the use of oxygen precipitates to control metal precipitation is a very attractive idea. A huge effort has been extended in the years since the realization of this effect to harness the potential of bulk oxygen precipitates to manage metal contamination. Such an approach to gettering is called internal gettering (IG).

The IG approach clearly side-steps the issues of particle contamination and damage longevity. But the use of oxygen precipitates as a gettering system can be a dangerous plaything. The engineering challenge is to insure that sufficient densities of oxygen precipitates are robustly and reliably produced in arbitrary IC processes and that a surface layer free of oxygen precipitates (a denuded zone) is produced in the wafer during the processing of the wafer. The denuded zone is required to avoid the presence of oxide precipitates in the near surface device layer in order to avoid detrimental effects of oxygen precipitates themselves. This is usually achieved by causing the dissolved oxygen in the wafer to out-diffuse at high temperature prior or during the nucleation of the oxygen precipitates in the bulk. This is often a costly additional process step which serves no other purpose than to prepare the wafer for use. A sufficient density in the bulk of the silicon wafer is required. This is to insure that, once metal precipitation starts at the oxide precipitate sites, these volume distributed sinks for metal diffusion are of a sufficiently high density to insure that a sufficient suppression of the metal concentration near the front surface in order to suppress metal precipitation there. It is known that oxygen precipitate densities of about 1-5 x 10 8 cm-3 are required for this [5,6]. An example of an ideal depth distribution of oxygen precipitates for gettering purposes is shown in Figure 3. Illustrated is a defect etched cross-section of a processed silicon wafer. The surface of the wafer is at the top. The depth of the defect free denuded zone is about 80 microns and the bulk density of oxygen precipitates is about 8 x 10 9 cm-3.

The engineering challenge of internal gettering

The engineering challenge to reliably produce such internal gettering structures has often proven to be illusive or expensive, or both. The general problem of the physics of the precipitation of oxygen in silicon has proven to be hugely complex and remains a still wildly unsatisfactorily resolved problem. In the 20 or so years since the discovery of the IG effect in silicon wafers, many scientists and engineers have struggled with the problem of precisely and reliably controlling the precipitation of oxygen in silicon which occurs during the processing of wafers into integrated circuits. This has been met with only partial success in the sense that the "defect engineering" of conventional silicon wafers is still, by and large, an empirical exercise. It consists largely of careful, empirical tailoring of wafer type (oxygen concentration, crystal growth method, and details of any additional pre-heat treatments, for example) to match the specific process details of the application to which they are submitted in order to achieve a good and reliable IG performance. In conventional silicon wafers the resultant oxygen precipitate density profiles are wildly dependent on the details the crystal growth process (primarily crystal cooling rates), the oxygen content of crystals and the details of the IC process to which the wafers are submitted. As a result, an entire industry-within-an-industry has sprung up built around attempts to control and tailor the oxygen precipitation performance of silicon wafers to specific processes. A large proportion of the complexity (and hence cost) of the manufacture of silicon wafers is centered on the specification and control of oxygen concentration and its behavior. Once a process is known to work for a given application a kind of process rigidity sets in. The potential for cost saving process improvements are reduced. Armies of expensive applications engineers and their counterparts at IC houses work on the tailoring of oxygen concentration and crystal growth processes to meet the needs of specific silicon applications. These are costs which the industry can no longer bear.


R. Falster, Z. Laczik, G.R. Booker, A.R. Bhatti and P. Török, in: Materials Research Society Symposium Proceedings Volume 262, Silicon Defect Engineering in Semiconductor Growth, Processing and Device Technology, (S. Ashok, J. Chevallier, K Sumino and E. Weber, eds., Pittsburgh, 1992), p. 945.
[2] R Falster, in the proceedings of the satellite symposium to ESSDERC 93 Grenoble, Electrochemical Society Proceedings Volume 93-15, Ed. by BO Kolbesen, P Stallhofer, Cor Claeys and F Tardif (1993), p.149.