Annealed Wafer

The Argon Annealed wafer is an advanced prime wafer which provides a defect-free surface region for high device yield and internal gettering for resistance to contamination. The combination of a nitrogen doped crystal and a high temperature furnace anneal in an argon ambient creates a defect free near-surface region, an oxygen denuded zone and a bulk oxygen precipitate density with internal gettering ability.

Argon annealed wafers are used in advanced CMOS technology processes and offer a yield advantage for polished wafers.

Argon annealed wafer cross section

COP-free and oxygen denuded zones for high device yield potential and oxygen precipitates in bulk for immediate gettering in device process.

Surface COP annihilation during high temperature argon annealing

Step 1: Oxygen above solubility limit. Oxide layer inside “bulk” COPs increases in thickness. COPs do not dissolve.

Step 2: Oxygen below solubility limit. Oxide layer inside “surface” COPs decreases in thickness. Once oxide layer no longer present, COPs first shrink and then dissolve through point defect interactions.

Physical model of COP annihilation: M.Hourai, et al., Defect in Silicon III, The Electrochemical Society PV 99-1, p. 372, 1999.

Impact of COPs on Device Yield

  • COPs are known to increase gate oxide defect density for oxide thickness ≥ 100 Å. Recent reports such as Itsumi’s suggest that COPs may not be as harmful to GOI for oxides < 100 Å.
  • Si wafer suppliers have generally confirmed Itsumi’s observations although recent SunEdison Semiconductor development programs appear to show a small but non-zero influence of COPs on defect density.
  • COPs are reported to decrease CMOS device yields by increasing field oxide leakage and junction leakage.
  • COPs interfere with the fabrication of high density, sub-100 nm gate length transistors when these fall into the surface pit associated with a COP.

Benefits of argon annealed wafers

COP-free surface zone ≥ 10μm

  • High GOI yield
  • Low surface light scattering counts (LLS’s)
  • High device yield potential

Out of Box Gettering (OOBG)

  • Annealing creates well defined denuded zone of ≥ 20μm
  • BMDs present in an annealed wafer ensure immediate gettering for low thermal budget processes
  • BMD density ≥ 5x108 defects/cm3
  • Meets all advanced wafer parametric requirements for global and local flatness, warp, surface roughness, and metals
  • Epi-like performance at lower cost

Annealed Literature & Other (PDFs)

Application Note 8/05