Glossary and Acronyms

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Silicon/Semiconductor Glossary (PDF, 177K) 

SunEdison Semiconductor and Industry-related Acronyms and Symbols (PDF, 62K)

A-C, D-F, G-I, J-L, M-O, P-R, S-U, V-X, Y-Z

6-Sigma: Capability index developed by Motorola measuring the number of standard deviations (a measure of variability) the mean is to the closest specification.


Å -- Angstrom

A-defects -- Dislocation loops in Silicon formed by agglomeration of interstitials

AA -- Atomic absorption

AE -- Acid Etch

AFM -- Atomic Force Microscopy

ALCVD -- Atomic Layer Chemical Vapor Deposition

AMC -- Barrel or batch type Epi reactor (Applied Materials)

APCVD -- Atmospheric-Pressure Chemical Vapor Deposition Furnace

ASIC -- Application Specific Integrated Circuit

ASM -- a single-chamber Epi reactor (ASM America)

ASTM -- American Standard Test Method

ASTM -- American Society for Testing and Materials

Acceptor: (p-type wafer) an impurity, as Gallium, Boron, etc., whose atoms in a semi-conductor produce positive, mobile charges while remaining bound in the crystal structure with a unit negative charge.

Acid: Any compound that can react with a base to form salt. Used mainly in Etching and Cleaning stages.

Alloy: Mixture of metals to increase durability.

Ambient: Natural state of the environment.

Ambient light: Normal room lighting.

Angle of Incidence: Angle in which the light goes into the wafer.

AOG: Axial Oxygen Gradient. Profile of oxygen concentration along the length of a crystal.

Argon: Inert, colorless, odorless gas used as the growing atmosphere in the crystal puller chamber; argon is backfilled after air purge.

Atmosphere: Standard barometric pressure equal to 760 torr. (1 micron = 1 millitorr, 1000 millitorr or 1000 microns = 1 torr, used as a measure of pressure).

Atomic Force Microscope (AFM): Atomic level surface mapping tool.

Autodoping: Dopant incorporated during the growth of an epitaxial layer from sources other than the dopant intentionally added to the vapor phase. Sources can include the back and front surfaces and edges of the substrate, and other substrates in the deposition assembly.


BESOI -- Bonded and Etch Back SOI

BGSOI -- Bonded and Grind Back SOI

BJT -- Bipolar Junction Transistor

BMD -- Bulk Micro-Defects or Bulk Microdefect Density (used almost exclusively as a measure of the oxygen precipitate density)

BOE -- Buffered Oxide Etch

BOX -- Buried Oxide Layer

BP -- Backside Polish

BV -- Breakdown Voltage

Bvox -- Breakdown Voltage-oxide

Backside: Side of the wafer that is NOT going to be polished. It is the side where the Enhanced Getter layer and/or LTO layer is placed if specified by the customer.

Backside OSF: Mechanical damage on the backside of the wafer that can precipitate stacking fault defects for gettering of impurities.

Baffle: Wafer or quartz used in furnaces to break course of gas flow at product wafers.

BDD: Bulk defect density.

BMD: Bulk Micro Defect.

Bonded Wafer: Two wafers bonded together: see SOI.

Bow: Bend or concavity of the wafer/slice. A measure of the lack of flatness of the wafer/slice.

BOX: Buried Oxide layer on SOI wafer.

Box-And-Whisker: Charting tool that visualizes data on a graph: the mean, middle 2 quartiles (50%), the upper (25%) and lower (25%) quartiles, and the largest and smallest values.

BSD: Backside damage, a process of mechanically damaging the backside of a wafer to increase gettering.

Bulk Precipitation: Defects in silicon used for gettering of impurities and can include dislocation loops, stacking fault defects, and oxygen precipitate defects.

Buried Layer: A diffused region that is covered with an epitaxial layer, subdiffused layer, or a diffusion under film.

Bvox: Breakdown voltage test of oxide layer grown on wafers, sister test to GOI.


oC -- Centigrade

oC/min -- Centigrade per minute

CD -- Critical Dimension

CE -- Caustic Etch

CIS -- CMOS Imaging System

cm-- Centimeter (0.01 meter)

CMOS -- Complementary Metal Oxide Semiconductor

CMP -- Chemical Mechanical Polishing

CO -- Carbon Monoxide

CO -- Carbon Dioxide

COO -- Cost of Ownership

COP's -- Crystal Originated Particles

CoQC -- Certificate Of Quality Conformance

CP -- Crystal Puller

CTL -- Charge Trap Layer

CV -- Capacity or capacitance voltage

CVD -- Chemical Vapor Deposition

CZ -- Czochralski method of pulling single crystal

Cantilever: Ceramic or silicon carbide rod or silicon carbide paddle that holds the quartz boats. This device is supported at one end. In this case, it is the door end and has the same function as a sled.

Capability Index: Value to measure how capable a product or process is at meeting a specification.

Carbon Beam: Length of carbon approximately 2" wide attached to the bottom of an ingot. In the slicing process the carbon allows the saw to cut completely through the silicon. The beam remains intact to hold the wafers until the preset number of wafers have been cut.

Carriers: Stainless steel apparatus used to contain wafers during the lapping process.

Cassette: Compact case designed to segregate slices for process handling and shipping.

Chamfer: Beveled edge.

Charge: Specified quantity of poly to be loaded into the crystal puller.

Cleanroom: Controlled areas with a low particle size/count where the latter part of wafer production takes place. The below table shows how classes are defined, with class 1 being the cleanest environment.

Class: # of particles allowed in a cubic foot of room air Particle Size
1 (means it can have no more than 1 particle) 0.5 micron or greater
10 0.5 micron or greater
100 (means it can have no more than 100 particles) 0.5 micron or greater
1000 0.5 micron or greater
10,000 0.5 micron or greater

Cleavage Plane: A break along crystal planes determined by crystal structure and always parallel to such a plane.

CMP: (Chemical-Mechical Polish) A process of removing surface material using chemical and mechanical means to achieve a mirror-like surface in preparation for subsequent processing.

Collimated Light: Light source in which the rays are parallel. Used for surface inspection of wafers.

Conductivity: A measure of the ease with which electrical carriers flow in a material: the reciprocal of Resistivity.

Conductivity Type: Defines the nature of the majority of carriers in the material: either N-type or P-type.

Contamination: Foreign matter in the silicon, other than polysilicon and dopant, that can cause loss of structure (atom alignment) during the growing process.

COP: Crystal Originated Pits.

Cp: Capability potential index which measures the width of two specifications in respect to six standard deviations.

Cpk: Statistical parameter used to compare product distribution to spec limits. A capability potential index measuring the distance from the mean to the nearest specification in respect to three standard deviations.

Crucible: Container made of quartz for holding the poly charge inside the crystal puller.

Crystal: A natural or synthetic semiconductor material whose atoms are arranged with some degree of geometric regularity. A solid composed of atoms, ions, or molecules arranged in a pattern that is periodic in three dimensions.

Crystal Puller: Machine designed to pull/grow electronic grade silicon under controlled parameters and within set specifications.

Crystallographic Orientation: There are three orientation planes in the silicon crystal: <100>, <110>, and <111>. The orientation of the wafer is classified by which orientation plane the surface of the wafer is parallel to. The surface might not be exactly parallel, but slightly different, and the difference is called the displacement angle or off angle orientation. The relationship between the crystal's orientation and the radius is marked by either a notch or a flat cut into the wafer.

Cubic Feet per Minute (CFM): Volumetric flow rate used to meter gases.

CVD (Chemical Vapor Deposition): Formation of a solid film on a substrate through the reaction of gas-phase reactants (precursors) that contain the required constituents.

Czochralski (CZ): Crystal growing process that was named after the inventor.



D-defects -- Very small voids in Silicon formed by agglomeration of vacancies

DIBL -- Drain Induced Barrier Lowering

DIC -- Differential Interference Contrast

DL -- Diffusion Length

DMOS -- Double-diffused MOS

DOE -- Design of Experiments

DOF -- Depth of Focus

DRAM -- Dynamic Random Access Memory

DSOD - Direct Surface Oxide Defect

DSP -- Double Sided Polish

DZ -- Denuded Zone (depth measured from the surface that is free of oxygen precipitates and which is denuded of interstitial oxygen (by out-diffusion))

Defect Free Region: The linear distance from the frontside wafer surface to the depth of the first bulk defect.

Degree: Unit of measuring angles when orienting an ingot.

Design of Experiments (DOE): Method to design, run and analyze an experiment to maximize information and minimize testing.

Diameter: Straight-line measurement drawn through the center of a circle or sphere from one side to the other.

Diffusion: A method of doping or modifying the characteristics of semiconductor material by "baking" wafers of the base semiconductor material in furnaces with controlled atmospheres of impurity materials.

Diffusion Length: The distance a front side free-electron or hole can travel through a crystal. This is proportional to the Lifetime of the crystal.

Dislocation: A class of one-dimensional, or line defects in silicon crystals.

DNZ (Denuded Zone Depth): The linear distance from the frontside wafer surface to the depth where the defect density appears nearly uniform.

Donor: Atom, usually an impurity in silicon, that acts as an electron source. It contributes an extra electron to the crystal structure. Most common is phosphorus.

Dopant: Element added to silicon decreasing its resistivity. Silicon, by itself does not conduct electricity. Boron is usually used for p-type and phosphorus is usually used for n-type.

Doping or Dopant: Chemical impurities added to polysilicon which will yield either n- or p-type silicon, depending on the specific dopant used.


eDRAM -- Embedded Dynamic Random Access Memory

EG -- Enhanced Gettering

EEPROM -- Electrically-erasable and Programmable Read-only Memory

EPROM -- Erasable and Programmable Read-only Memory

EOT -- Equivalent Oxide Thickness

EPI -- Epitaxy

ESF -- Epi Stacking Fault

Edge Crown: The difference between the surface elevation 1/8" (3.2mm) from the edge of the slice and the elevation of the slice edges exposed in microns (associated with epi layer deposition).

Edge Exclusion: Narrow band on the outside edge of the wafer that does not have an oxide coating.

Edge Grinding: Process that bevels the edges of the slices to strengthen them.

Ellipsometer: Optical measuring device used to measure oxide and nitride thickness, as well as, the index of refraction.

Epi: (epitaxial or epitaxy process) Depositing a thin layer of silicon atoms onto a wafer by condensing a controlled amount of silicon gas (silane) onto the polished surface of the wafer in a temperature-controlled environment.

Epitaxial Layer: The layer or layers of semiconductor material having the same crystalline orientation as the host substrate on which it is grown.

Endcone or Bottom: Gradual decreases in diameter until the silicon forms a point at the end of the growing/pulling process. As a rule of thumb, the bottom/endcone should be grown the length of the rod's diameter to allow for shock back or undesirable structure.

Etch: To remove or dissolve surface contamination, work-damaged material (polishing), and to control thickness by chemical action with strong acid and alkaline compounds.

Etch - Mirror: Used to create a clean, shiny finish for visual inspection and resistivity measurements.

Etch - Preferential: An etch that exhibits an accelerated etch rate along specific crystallographic planes.

Etch Rate: Rate of silicon removal in microns per minute.


FBE -- Floating Body Effect

FET -- Field Effect Transistor

FD-SOI -- Fully Depleted Silicon-on-Insulator

FPD -- Flow Pattern Defect (ref. Crystal)

FPD -- Focal Plane Deviation (ref. Mechanical flatness)

FRAM -- Ferroelectric Random Access Memory

FTIR -- Fourier Transform Infra-Red Spectroscopy

FZ -- Float Zone method of Crystal Pulling

Face: Parallel lines along the surface of the crystal, also known as growth lines or ZD, zero defect, lines.

Flat: Straight edge on the wafer's outer perimeter. It is used to identify certain characteristics. (AKA the JLS).

Flat (major): May be the only flat (straight edge) on the wafer. If there is more than one flat then it is the longest flat on the perimeter of the wafer.

Flat (minor): Shortest flat (straight edge) on the wafer.

Flatness: The maximum deviation of the wafer surface from a flat plane. Flatness measurement is usually done with the backside held to a flat surface (a vacuum chuck) and excludes linear thickness variations.

Focal Plane: That plane whose normal provides the shortest distance between the absolute maximum and absolute minimum on the wafer surface.

Focal Plane Deviation (FPD): Maximum deviation of the wafer surface above and below the focal plane.

FTIR: Fourier Transform Infrared, a means of measuring oxygen or carbon levels in the crystal.



GBIR -- Global flatness, back-referenced

GeOI -- Germanium-on-Insulator

GFA -- Gas Fusion Analysis

GOI -- Gate Oxide Integrity

GTIR -- Global Total Indicated Reading

GUI -- Graphical User Interface

Gettering: Gettering is a process that attracts contaminents and traps defects when the wafers are heated. Can be initiated through mechanical damage or interstial oxygen. Extrinsic gettering is caused by BSD. Intrinsic gettering is caused by interstial oxygen.

Global Flatness: Overall flatness of the wafer.

Grind: Abrade/remove material by grinding; rod diameter reduction method to specifications and for flattening.

GFA: Gas Fusion Analysis, a means of testing oxygen or carbon levels in the crystal.

GOI: Gate Oxide Integrity


H2 -- Hydrogen gas

H2O2 -- Hydrogen Peroxide

HCl -- Hydrogen Chloride

HF -- Hydrofluoric Acid

HMOS -- High-performance MOS

HR -- High Resistivity

HZ -- Hot Zone

Haze: Light scattering caused by microscopic surface irregularities (such as a high concentration of pits, mounds, small ridges, particles, etc.) on epitaxial wafers or polished slices.

Hillocks: Defect in the surface of the wafer resembling a hill; cannot be seen with the naked eye.


IC -- Integrated Circuits

IDM -- Integrated Device Manufacturer

IG -- Internal Gettering

IGBT -- Insulated Gate Bipolar Transistor

IQC -- Incoming Quality Control

ISO -- International Standards Organization

ITOX -- Internal Oxidation

Ingot: A semiconductor grown cylinder, polycrystalline or single crystal, generally of irregular diameter or in the as-grown state.

Integrated circuits: Tiny complex electronic components and their connections produced on a silicon slice.

Interstitial: Relating to crystalline compound in which small atoms or ions of a nonmetal occupy holes between the larger metal atoms and ions in the crystal lattice.



JFET -- Junction Field Effect Transistor

JLS (Joseph Larry Schaefer): Method of physically identifying a wafer. Major flats, minor flats and notches are ground on the silicon rod before it is cut. These markings identify the molecular orientation.


kg -- Kilogram

kN -- Kilo Newton

KOH -- Potassium Hydroxide

kP -- Kilo Pascal

KSIE -- Thousand Square Inch Equivalent

Kerf:The notch left by a saw cut; the width of a saw cut. Kerf Loss: The amount of material lost while slicing wafers. The kerf is the cut and swarf is the chips and fillings from the kerf.


LAD -- Large Area Defect

Lg -- Transistor Gate Length

LLS -- Localized Light Scatterers

LLPD's -- Large Light Point Defects

LPCVD -- Low Pressure Chemical Vapor Deposition

LPD's -- Light Point Defects

LPD-E -- Light Point Defect, class E (a KLA-Tencor SP1 defect class)

LPD-N -- Light Point Defect, class N (a KLA-Tencor SP1 defect class)

LPD-S -- Light Point Defect, class S (a KLA-Tencor SP1 defect class)

LPE -- Liquid Phase Epitaxy

LSE -- Latex Sphere Equivalent particle size

LSI -- Large-scale Integration

LSTD -- Laser Scattering Tomographic Detection

LTO -- Low Temperature Oxide

Lapping: Process to remove controlled amounts of silicon from the slice using a lapping compound. This process removes saw damage and positively impacts the slice's flatness.

Laser mark: Method of identification required by some customers. Series of letters and numbers inscribed onto the wafer by laser.

Lifetime: The average time a free-electron or hole can exist in a crystal, measured in seconds. Lifetime may vary within a crystal: bulk lifetime within the crystal and surface lifetime at, of course, the surface.

Linear Thickness Variation: Thickness variation within a slice whose front and back surfaces can be represented by two, nonparallel planes.

Local or Site Flatness: Flatness of specifically defined areas on the slice.

Lot: Group of wafers going to the same area with the same identities and are to be processed together.

Low Temperature Oxide (LTO): Sealant to keep the dopant in the wafer when it goes through the Epi process. It is applied in Furnace/Enhanced Gettering Area.

LPCVD: Low Pressure CVD, deposits a layer of polysilicon to the wafer, later removed by polishing. A backside layer can act as a gettering agent.

LPD: Light Particle Defect, sometimes known as particles.



MBE -- Molecular Beam Epitaxy

MCU -- Micro Controller Unit

MDZ -- Magic Denuded Zone (gettering)

MEMS -- Micro-ElectroMechanical System

MIM -- Metal-Insulator-Metal

MLD -- Modified Low Dose

mm -- 1/1000 of a meter and 0.03937 inch

mm/min -- millimeters per minute

MNOS -- Metal Nitride Oxide Semiconductor

MOCVD -- MetalOrganic Chemical Vapor Deposition

MODFET -- Modulation-Doped Field Effect Transistor

MOS -- Metal Oxide Semiconductor

MOSFET -- Metal Oxide Semiconductor Field Effect Transistor

MPU -- Micro Processing Unit

MRAM -- Magnetoresistive Random Access Memory

MSI -- Medium-scale Integration

MSIE -- Million Square Inch Equivalent

Melt: The pure, molten silicon from which single crystal silicon is grown in a crystal pulling furnace during the Czochralski process.

Meltdown: Changing a polysilicon charge from a solid to a liquid state by heating it in the crystal puller.

Micron: A unit of length, 1/1,000,000 (one millionth) of a meter.

MOScap: Test structure used for Bvox, GOI, VTW, and Zerbst tests. Capacitor structure: silicon wafer/gate oxide/polysilicon gate.


N -- Silicon doped to create excess negative charge carriers (electrons)

N+ -- Heavily doped, N-type silicon

NT -- Nanotopography

N2 -- Nitrogen gas

nm -- nanometers

NMOS -- N-channel Metal Oxide Semiconductor

NPT -- Non-Punch Through

Nanotopology: Surface variations over a small area

N-Type: Property of the silicon semiconductor material. Doping with donor atoms increases the density of negative charge carriers (electrons) in the conduction band and produces an N-type semiconductor.

Neck: Portion of the crystal below the seed and above the taper. The first growth step in a crystal.


O2 -- Oxygen

Oi -- Interstitial Oxygen

OISF -- Oxidation-Induced Stacking Fault

OPP -- Optical Precipitate Profiler

OUM -- Ovonics Unified Memory

Ohm: Unit of electrical resistance.

Oi: Interstitial Oxygen.

Opposite End (OE): End of the grown crystal rod. Known more formally as the 'tang' portion of the rod.

Optical Comparator: Instrument held close to the wafer's edge for evaluation of the edge grinding process.

Optical Precipitation Profiler (OPP): Non-destructive measurement of bulk defects.

Orientation: Customer specified atom alignment in their crystal. Two main atom alignment plane patterns that are grown: 1-0-0 and 1-1-1.

OSF: Oxidation Stacking Faults.

Oxidation: Act of forming oxides. In silicon, oxygen impurities form oxides.



P -- Silicon doped to create excess positive charge carriers (holes)

P- -- Lightly doped P-type silicon wafer

P+ -- Heavily doped P-type silicon wafer

P/P+ -- Lightly doped P-type epi layer on a heavily doped P-type substrate

P/P- -- Lightly doped P-type epi layer on a lightly doped P-type substrate

P-band -- Anomalous oxygen precipitation region in vicinity of the vacancy/interstitial boundary

PD-SOI -- Partially Depleted Silicon-on-Insulator

PECVD -- Plasma Enhanced Chemical Vapor Deposition Furnace

PFRAM -- Polymeric Ferroelectric Random Access Memory

PFZ -- Precipitate Free Zone (depth measured from the surface that is free of oxygen precipitates but not necessarily depleted in interstitial oxygen)

PMOS -- P-channel Metal Oxide Semiconductor

PPB -- Parts Per Billion

PPC -- Post Polish Clean

PPE -- Personal Protective Equipment

PPM -- Parts Per Million

PPMA -- Parts Per Million Atomic

PPMD -- Parts Per Million Defective

PPT -- Parts Per Trillion

PROM -- Programmable Read-only Memory

PT -- Punch Through

P/V -- Peak to Valley measurement

PZT -- Lead Zirconate Titanate

P- : Typically P-type material with a resistance greater than 1

P+ : Typically P-type material with a resistance less than 1

P++ : P-type material highly doped with boron with a resistivity between 0.005 and 0.010

P-Type: Material that has free-holes created by the proper dopant.

Parts Per Million Defective (PPMD): On average, of one million parts produced, the number that are defective.

Polished Surface: The surface of a semiconductor slice that has received extensive chemical/mechanical operations to result in a mirror-like finish. This surface will then become the basis for subsequent device fabrication.

Poly Coating: During deposition stage of the Enhanced Gettering process, a fine grain polycrystalline silicon coating is deposited on the back side of wafer. It enhances the substrate properties the customer requires.

Polycrystalline silicon (poly): The raw material used in the Czochralski process in crystal pulling. The silicon lattice structure is randomly oriented in poly.

PP Box: Poly Propylene Box, the box used to store and ship polished wafers.

Precipitates: Football shaped etch artifacts when decorative etched with Wright Etch.



RAM -- Random Access Memory

RF -- Radio Frequency

RFCMOS -- Radio-Frequency Complementary Metal Oxide Semiconductor

ROM -- Read-only Memory

RSD -- Raised Source/Drain

RTA -- Rapid Thermal Anneal

RTP -- Rapid Thermal Process

Resistivity: How much the silicon resists conducting electricity. The more it resists, the higher the resistivity. The less it resists, the lower the resistivity. Customers specify the resistivity level they want.

Rod: Ground crystal from Grinding. The rod is the raw material for Slicing.

ROG: Radial Oxygen Gradient, change in the concentration of oxygen from the center of a crystal to the edge.

RRG: Radial Resistivity Gradient, the difference between the resistivity at the center of a semiconductor slice and the value at a point, or at several symmetrically located points, away from the center of the slice, typically at half the slice radius or near the slice edge. This difference is expressed as a percentage of the center value.



SAC -- Submicron Application Crystal

SBIR -- Site flatness, back-referenced

SBSD -- Soft Backside Damage

SC1 -- 1st cleaning bath in the standard "RCA clean" sequence, consisting of NH4OH / H202/ H20 solution designed to remove particles from Si surface

SC2 -- 2nd cleaning bath in the standard "RCA clean" sequence, consisting of HCl / H202/ H20 solution designed to remove metals from Si surface

SCE -- Short Channel Effects

SEM -- Scanning Electron Microscope

SFQR -- Site flatness, best-fit, front-referenced

SFSR -- Site flatness, best-fit, front-referenced, scanning site

SGOI - Strained Si on SiGe on Insulator

Si -- Silicon

SIE -- Square Inch Equivalent

SIMOX -- Separation by Implantation of Oxygen

SIMS -- Secondary Ion Mass Spectroscopy

SiO -- Silicon Monoxide

SiO2 -- Silicon Dioxide

SIP -- Single In-line Package

SIRM -- Scanning Infra-red Microscope

SoC -- System-on-a-Chip

SOI -- Silicon-on-Insulator

SOS -- Silicon-on-Sapphire

SPT -- Soft Punch Through

SPV -- Surface Photovoltage

SRAM -- Static Random Access Memory

SRP -- Spreading Resistance Probe or Spreading Resistance Profile

SSI -- Small-scale Integration

sSi -- Strained Silicon

SSIS -- Surface Scanning Inspection System

SSOI -- Strained Silicon directly on Insulator

SSP -- Single Side Polish

STD -- Standard

STD CZ -- Standard Czochralski-grown Crystal

STI -- Shallow Trench Isolation

STIR -- Site TIR (Total Indicated Reading)

Secondary Ion Mass Spectrometry (SIMS): Dopant and impurity depth profiling, done by outside vendors for SunEdison Semiconductor.

Seed End (SE): Beginning end of a grown silicon crystal rod.

Seed Crystal: The seed is the starting point for growing the ingot. It must have the same crystal orientation as desired for the resulting ingot.

SEMI: Semiconductor Equipment and Materials Institute. Sets specifications for the semiconductor industry.

Silicon: Tetravalent nonmetallic element that occurs combined as the most abundant element next to oxygen in the earth's crust and is used in alloys and electronic devices.

Single Crystal: When the atoms in the crystal are all aligned in the same way.

Slip: A process of plastic deformation in which one part of the crystal undergoes a shear displacement relative to another in a fashion that preserves the crystallinity of the material. The direction is on a specific crystallographic plane.

Slug: Thick piece of silicon, usually a wedge cut, used to test the material characteristics for customer specs.

Slurry: Solid suspension in liquid used for slicing, lapping, and polishing.

SOI: Silicon on Insulator, usually achieved by bonding two wafers, one of which has oxide on top.

SRP - Spreading Resistance Profiling: The resistance measured between the conductive metal of a point probe and a large area, relatively low-resistance semiconductor contact, dominated by the resistivity of the semiconductor volume close to the problem.

Stacking Faults: Pyramid shaped imperfections in the silicon wafer.

Substrate: Basic surface on which a material adheres. A single-crystal slice that is the basis for subsequent processing operations, such as epi layer deposition, diffusion, ion implants, etc.

Surface Photovoltage (SPV): Test for recombination minority carrier lifetime.

Swirl: Shallow pits looked for during visual inspection. Helical or concentric features that are visible to the unaided eye after preferential etch, and appear to be discontinuous under 150x magnification.


T -- Temperature

TCS -- Trichlorosilane

TEM -- Transmission Electron Microscope

TIR -- Total Indicated Reading

TOX -- Gate Oxide Thickness

Tsoi -- Thickness of SOI top Si layer

TSOP -- Thin Small Outline Package

TTV -- Total Thickness Variation

Taper: A measure of the flatness of a wafer, taper being thicker at the edges than at the center.

Thickness: Cross sectional depth of a silicon slice measured in mils (1 mil = 0.001 inch).

TIR: Total Indicator Reading, the distance between the highest and lowest point on the wafer surface measured normal to the focal plane.

Total Thickness Variation (TTV): variation of thickness from the center and both sides of the wafer.


ULSI-- Ultra Large-scale Integration



v/G -- v: growth rate (crystal pulling rate), G: vertical temperature gradient at melt/solid interface

VI -- Vacancy Interstitial

VLSI -- Very Large-scale Integration

VPE-- Vapor Phase Epitaxy


WRFTIR -- Whole Rod Fourier Transform Infra-Red Spectroscopy

Warp: Maximum distance from the lowest point to the highest point on the wafer's surface.


XTL -- Crystal



ZD -- Zero Dislocation

Zero Dislocation: perfect crystalline structure in a silicon crystal. The desirable condition of symmetrically oriented and arranged atoms having a definite and characteristic internal structure.